Cross Reference: /xsrc/external/mit/xf86-video-nsc/dist/src/gfx/disp

Lines Matching refs:READ_REG32
290       READ_REG32(MDC_UNLOCK);
307       READ_REG32(MDC_UNLOCK);
327    dcfg = READ_REG32(MDC_DISPLAY_CFG) & ~(MDC_DCFG_DISP_MODE_MASK |
329    lock = READ_REG32(MDC_UNLOCK);
433    unlock = READ_REG32(MDC_UNLOCK);
438    gcfg = READ_REG32(MDC_GENERAL_CFG);
439    dcfg = READ_REG32(MDC_DISPLAY_CFG);
520    temp = READ_REG32(MDC_DV_CTL);
533    vid_buf_size = READ_REG32(MDC_LINE_SIZE) & 0xFF000000;
814    unlock = READ_REG32(MDC_UNLOCK);
819    dcfg = READ_REG32(MDC_DISPLAY_CFG);
820    vactive = READ_REG32(MDC_V_ACTIVE_TIMING);
821    vblank = READ_REG32(MDC_V_BLANK_TIMING);
859    unsigned long lock = READ_REG32(MDC_UNLOCK);
861    value = READ_REG32(MDC_GFX_PITCH) & 0xFFFF0000;
876    value = READ_REG32(MDC_GENERAL_CFG);
906    lock = READ_REG32(MDC_UNLOCK);
1008    unlock = READ_REG32(MDC_UNLOCK);
1009    gcfg = READ_REG32(MDC_GENERAL_CFG);
1101    unlock = READ_REG32(MDC_UNLOCK);
1214    unlock = READ_REG32(MDC_UNLOCK);
1215    gcfg = READ_REG32(MDC_GENERAL_CFG);
1268    unsigned long lock = READ_REG32(MDC_UNLOCK);
1333    if (READ_REG32(MDC_FB_ST_OFFSET) & 0x0FFFFFFF)
1346    temp = READ_REG32(MDC_DV_CTL);
1351    unlock = READ_REG32(MDC_UNLOCK);
1352    gcfg = READ_REG32(MDC_GENERAL_CFG);
1377    unlock = READ_REG32(MDC_UNLOCK);
1378    gcfg = READ_REG32(MDC_GENERAL_CFG);
1434    lock = READ_REG32(MDC_UNLOCK);
1458    lock = READ_REG32(MDC_UNLOCK);
1462    line_delta = READ_REG32(MDC_GFX_PITCH) & 0x0000FFFF;
1497    lock = READ_REG32(MDC_UNLOCK);
1498    buf_size = READ_REG32(MDC_LINE_SIZE) & 0xFF80FFFF;
1523    lock = READ_REG32(MDC_UNLOCK);
1524    gcfg = READ_REG32(MDC_GENERAL_CFG);
1565    lock = READ_REG32(MDC_UNLOCK);
1566    gcfg = READ_REG32(MDC_GENERAL_CFG);
1567    dcfg = READ_REG32(MDC_DISPLAY_CFG);
1602    lock = READ_REG32(MDC_UNLOCK);
1603    value = READ_REG32(MDC_LINE_SIZE) & 0x00FFFFFF;
1604    yuv_420 = READ_REG32(MDC_GENERAL_CFG) & MDC_GCFG_YUVM;
1645    lock = READ_REG32(MDC_UNLOCK);
1673    lock = READ_REG32(MDC_UNLOCK);
1703    lock = READ_REG32(MDC_UNLOCK);
1729    lock = READ_REG32(MDC_UNLOCK);
1762    unlock = READ_REG32(MDC_UNLOCK);
1763    gcfg = READ_REG32(MDC_GENERAL_CFG);
1787    if (READ_REG32(MDC_DISPLAY_CFG) & MDC_DCFG_TGEN)
1805    if (READ_REG32(MDC_LINE_CNT_STATUS) & MDC_LNCNT_VNA)
1851    modeBytesPerScanline = (READ_REG32(MDC_GFX_PITCH) & 0x0000FFFF) << 3;
1998    return ((unsigned short)(READ_REG32(MDC_GFX_PITCH) & 0x0000FFFF) << 3);
2474    return ((READ_REG32(MDC_LINE_SIZE) & 0x7FF) << 3);
2489    return ((unsigned short)((READ_REG32(MDC_H_ACTIVE_TIMING) & 0x0FF8) + 8));
2504    return ((unsigned short)((READ_REG32(MDC_H_SYNC_TIMING) & 0x0FF8) + 8));
2519    return ((unsigned short)(((READ_REG32(MDC_H_SYNC_TIMING) >> 16) & 0x0FF8) +
2535    return ((unsigned short)(((READ_REG32(MDC_H_ACTIVE_TIMING) >> 16) & 0x0FF8)
2551    return ((unsigned short)((READ_REG32(MDC_V_ACTIVE_TIMING) & 0x07FF) + 1));
2566    return ((unsigned short)(((READ_REG32(MDC_V_SYNC_TIMING) >> 16) & 0x07FF) +
2582    return ((unsigned short)(((READ_REG32(MDC_V_ACTIVE_TIMING) >> 16) & 0x07FF)
2600    unsigned long dcfg = READ_REG32(MDC_DISPLAY_CFG);
2645 	    (unsigned short)(READ_REG32(MDC_LINE_CNT_STATUS) &
2648 	  (unsigned short)(READ_REG32(MDC_LINE_CNT_STATUS) &
2666    return (READ_REG32(MDC_FB_ST_OFFSET) & 0x0FFFFFFF);
2681    return (READ_REG32(MDC_CURS_ST_OFFSET) & 0x0FFFFFFF);
2702    return ((unsigned short)((READ_REG32(MDC_H_BLANK_TIMING) & 0x0FF8) + 8));
2717    return ((unsigned short)(((READ_REG32(MDC_H_BLANK_TIMING) >> 16) & 0x0FF8)
2733    return ((unsigned short)((READ_REG32(MDC_V_BLANK_TIMING) & 0x07FF) + 1));
2748    return ((unsigned short)((READ_REG32(MDC_V_SYNC_TIMING) & 0x07FF) + 1));
2763    return ((unsigned short)(((READ_REG32(MDC_V_BLANK_TIMING) >> 16) & 0x07FF)
2783    *palette = READ_REG32(MDC_PAL_DATA);
2804       palette[i] = READ_REG32(MDC_PAL_DATA);
2820    return (READ_REG32(MDC_GENERAL_CFG) & MDC_GCFG_CURE);
2835    return ((READ_REG32(MDC_CURSOR_X) & 0x07FF) |
2836 	   ((READ_REG32(MDC_CURSOR_Y) << 16) & 0x03FF0000));
2851    return (((READ_REG32(MDC_CURSOR_X) >> 11) & 0x03F) |
2852 	   ((READ_REG32(MDC_CURSOR_Y) << 5) & 0x3F0000));
2872    return READ_REG32(MDC_PAL_DATA);
2887    return (READ_REG32(MDC_GENERAL_CFG) & MDC_GCFG_ICNE);
2902    return (READ_REG32(MDC_ICON_ST_OFFSET) & 0x0FFFFFFF);
2917    return (READ_REG32(MDC_ICON_X) & 0x07FF);
2937    return READ_REG32(MDC_PAL_DATA);
2952    if (READ_REG32(MDC_GENERAL_CFG) & MDC_GCFG_CMPE)
2970    return (READ_REG32(MDC_CB_ST_OFFSET) & 0x007FFFFF);
2987    pitch = (unsigned short)(READ_REG32(MDC_GFX_PITCH) >> 16);
3005    size = (unsigned short)((READ_REG32(MDC_LINE_SIZE) >> 16) & 0x7F) - 1;
3024    offset = READ_REG32(MDC_PHY_MEM_OFFSET) & 0xFF000000;
3028    valid = (int)READ_REG32(MDC_DV_ACC) & 2;
3050    return (READ_REG32(MDC_VID_Y_ST_OFFSET) & 0x0FFFFFFF);
3072    *yoffset = (READ_REG32(MDC_VID_Y_ST_OFFSET) & 0x0FFFFFFF);
3073    *uoffset = (READ_REG32(MDC_VID_U_ST_OFFSET) & 0x0FFFFFFF);
3074    *voffset = (READ_REG32(MDC_VID_V_ST_OFFSET) & 0x0FFFFFFF);
3092    unsigned long pitch = READ_REG32(MDC_VID_YUV_PITCH);
3113    return (READ_REG32(MDC_VID_DS_DELTA) >> 18);
3131    return ((int)((READ_REG32(MDC_GENERAL_CFG) >> 19) & 1));
3151    return ((READ_REG32(MDC_LINE_SIZE) >> 21) & 0x000007FF);