Lines Matching defs:chip
40 RIVA_HW_INST *chip
43 return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x000006B0/4] & 0x01));
47 RIVA_HW_INST *chip,
52 VGA_WR08(chip->PCIO, 0x3D4, 0x11);
53 cr11 = VGA_RD08(chip->PCIO, 0x3D5);
56 VGA_WR08(chip->PCIO, 0x3D5, cr11);
61 RIVA_HW_INST *chip,
65 VGA_WR08(chip->PVIO, 0x3C4, 0x06);
66 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
67 vgaLockUnlock(chip, Lock);
71 RIVA_HW_INST *chip,
76 current = chip->CurrentState->cursor1;
77 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |
79 VGA_WR08(chip->PCIO, 0x3D4, 0x31);
80 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
523 RIVA_HW_INST *chip
530 pll = chip->PRAMDAC[0x00000504/4];
532 MClk = (N * chip->CrystalFreqKHz / M) >> P;
537 sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64;
577 RIVA_HW_INST *chip
589 if (chip->CrystalFreqKHz == 13500)
604 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
608 N = (VClk << P) * M / chip->CrystalFreqKHz;
610 Freq = (chip->CrystalFreqKHz * N / M) >> P;
635 RIVA_HW_INST *chip,
656 CalcVClock(dotClock, &VClk, &m, &n, &p, chip);
662 chip);
687 chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
690 chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
693 chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
696 chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
699 chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
702 RIVA_HW_INST *chip
708 RIVA_HW_INST *chip,
722 chip->PFB[0x00000200/4] = state->config;
745 chip->PRAMIN[0x00000502 + i] = (i << 12) | 0x03;
746 chip->PGRAPH[0x00000630/4] = state->offset;
747 chip->PGRAPH[0x00000634/4] = state->offset;
748 chip->PGRAPH[0x00000638/4] = state->offset;
749 chip->PGRAPH[0x0000063C/4] = state->offset;
750 chip->PGRAPH[0x00000650/4] = state->pitch;
751 chip->PGRAPH[0x00000654/4] = state->pitch;
752 chip->PGRAPH[0x00000658/4] = state->pitch;
753 chip->PGRAPH[0x0000065C/4] = state->pitch;
756 UpdateFifoState(chip);
761 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
762 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
763 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
764 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
765 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
766 VGA_WR08(chip->PCIO, 0x03D5, state->screen);
767 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
768 VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
769 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
770 VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
771 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
772 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
773 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
774 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
775 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
776 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
777 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
778 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
779 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
780 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
781 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
782 VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
784 chip->PRAMDAC[0x00000508/4] = state->vpll;
785 chip->PRAMDAC[0x0000050C/4] = state->pllsel;
786 chip->PRAMDAC[0x00000600/4] = state->general;
791 chip->PCRTC[0x00000140/4] = 0;
792 chip->PCRTC[0x00000100/4] = chip->VBlankBit;
796 chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01;
800 chip->CurrentState = state;
804 chip->FifoFreeCount = 0;
806 chip->FifoEmptyCount = chip->Rop->FifoFree;
811 RIVA_HW_INST *chip,
818 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
819 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5);
820 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
821 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5);
822 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
823 state->screen = VGA_RD08(chip->PCIO, 0x03D5);
824 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
825 state->pixel = VGA_RD08(chip->PCIO, 0x03D5);
826 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
827 state->horiz = VGA_RD08(chip->PCIO, 0x03D5);
828 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
829 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
830 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
831 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
832 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
833 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);
834 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
835 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);
836 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
837 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);
838 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
839 state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
840 state->vpll = chip->PRAMDAC[0x00000508/4];
841 state->pllsel = chip->PRAMDAC[0x0000050C/4];
842 state->general = chip->PRAMDAC[0x00000600/4];
843 state->config = chip->PFB[0x00000200/4];
844 state->offset = chip->PGRAPH[0x00000630/4];
845 state->pitch = chip->PGRAPH[0x00000650/4];
850 RIVA_HW_INST *chip,
861 chip->LockUnlock(chip, 0);
865 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);
867 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);
869 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);
870 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));
871 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);
872 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));
876 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);
877 VGA_WR08(chip->PCIO, 0x3C0, 0x13);
878 VGA_WR08(chip->PCIO, 0x3C0, pan);
888 RIVA_HW_INST *chip
892 * Fill in chip configuration.
894 if (chip->PFB[0x00000000/4] & 0x00000020)
896 if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20)
897 && ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02))
902 chip->RamBandwidthKBytesPerSec = 800000;
903 switch (chip->PFB[0x00000000/4] & 0x03)
906 chip->RamAmountKBytes = 1024 * 4;
909 chip->RamAmountKBytes = 1024 * 2;
912 chip->RamAmountKBytes = 1024 * 8;
918 chip->RamBandwidthKBytesPerSec = 1000000;
919 chip->RamAmountKBytes = 1024 * 8;
927 chip->RamBandwidthKBytesPerSec = 1000000;
928 switch (chip->PFB[0x00000000/4] & 0x00000003)
931 chip->RamAmountKBytes = 1024 * 8;
934 chip->RamAmountKBytes = 1024 * 4;
937 chip->RamAmountKBytes = 1024 * 2;
941 chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
942 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
943 chip->VBlankBit = 0x00000100;
944 chip->MaxVClockFreqKHz = 256000;
946 * Set chip functions.
948 chip->Busy = nv3Busy;
949 chip->ShowHideCursor = ShowHideCursor;
950 chip->CalcStateExt = CalcStateExt;
951 chip->LoadStateExt = LoadStateExt;
952 chip->UnloadStateExt = UnloadStateExt;
953 chip->SetStartAddress = SetStartAddress;
954 chip->LockUnlock = nv3LockUnlock;
961 RIVA_HW_INST *chip = &pRiva->riva;
963 nv3GetConfig(chip);
967 chip->Rop = (RivaRop *)&(chip->FIFO[0x00000000/4]);
968 chip->Clip = (RivaClip *)&(chip->FIFO[0x00002000/4]);
969 chip->Patt = (RivaPattern *)&(chip->FIFO[0x00004000/4]);
970 chip->Pixmap = (RivaPixmap *)&(chip->FIFO[0x00006000/4]);
971 chip->Blt = (RivaScreenBlt *)&(chip->FIFO[0x00008000/4]);
972 chip->Bitmap = (RivaBitmap *)&(chip->FIFO[0x0000A000/4]);
973 chip->Line = (RivaLine *)&(chip->FIFO[0x0000C000/4]);