Lines Matching defs:Enable
251 * 1: Enable */
257 * 1: Enable */
348 /* PRIM_HI_CTRL[0] - Hardware Icon (HI) Enable */
356 /* HI_CONTROL[0] - Hardware Icon (HI) Enable */
444 /* 3X5.6A[7] - Second Display Channel Enable */
542 * 1: Enable */
612 /* HI_CONTROL[0] - Hardware Icon (HI) Enable */
620 /* HI_CONTROL[0] - Hardware Icon (HI) Enable */
787 "Enable Register: 0x%02X\n", temp));
797 "Enable Register: 0x%02X\n", temp));
838 * 1: Enable */
856 * 1: Enable
872 * 1: Enable
958 * 1: Enable
967 * 3C5.15[1] - Extended Display Mode Enable
969 * 1: Enable
976 * 1: Enable clock gating
979 * 1: Enable clock gating
982 * 1: Enable clock gating
985 * 1: Enable clock gating
988 * 1: Enable clock gating
991 * 1: Enable clock gating
994 * 1: Enable clock gating */
997 /* 3C5.1A[7] - Read Cache Enable
999 * 1: Enable
1009 * 3C5.1A[3] - Extended Mode Memory Access Enable
1011 * 1: Enable
1106 * 1: Enable */
1118 * 1: Enable
1125 /* 3X5.6B[3] - Simultaneous Display Enable
1127 * 1: Enable */
1251 * 3X5.32[2] - Display End Blanking Enable
1253 * 1: Enable
1259 * 1: Enable
1269 * 1: Enable
1272 * 1: Enable
1277 * 1: Enable
1298 * 1: Enable
1461 * 3X5.32[2] - Display End Blanking Enable
1463 * 1: Enable
1469 * 1: Enable
1479 * 1: Enable
1482 * 1: Enable
1487 * 1: Enable
1808 ViaSetCLE266APrimaryFIFO(ScrnInfoPtr pScrn, Bool Enable)
1814 "ViaSetCLE266APrimaryFIFO: %d\n", Enable));
1820 if (Enable)
2670 /* 3X5.6A[7] - Second Display Channel Enable
2672 * 1: Enable
2680 * 1: Enable
2681 * 3X5.6A[1] - LCD Gamma Enable
2683 * 1: Enable
2684 * 3X5.6A[0] - LCD Pre-fetch Mode Enable
2686 * 1: Enable */
2722 /* 3X5.79[0] - LCD Scaling Enable
2724 * 1: Enable */
3825 /* Enable IGA1 */
4239 /* Enable IGA2 display channel. */