Lines Matching defs:xl
78 #define MPEGIN(xl,reg) \
79 *((volatile CARD32 *)(((CARD8 *)(xl)->mmioAddress) + 0xc00 + (reg)))
163 #define WAITFLAGS(xl, flags) \
164 (xl)->curWaitFlags |= (flags)
165 #define BEGIN_RING_AGP(xl,size) \
167 if ((xl)->agp_pos > (LL_AGP_CMDBUF_SIZE-(size))) { \
168 agpFlush(xl); \
171 #define OUT_RING_AGP(xl, val) \
172 (xl)->agp_buffer[(xl)->agp_pos++] = (val)
173 #define OUT_RING_QW_AGP(xl, val1, val2) \
175 (xl)->agp_buffer[(xl)->agp_pos++] = (val1); \
176 (xl)->agp_buffer[(xl)->agp_pos++] = (val2); \
179 #define LL_HW_LOCK(xl) \
181 DRM_LOCK((xl)->fd,(xl)->hwLock,*(xl)->drmcontext,0); \
183 #define LL_HW_UNLOCK(xl) \
185 DRM_UNLOCK((xl)->fd,(xl)->hwLock,*(xl)->drmcontext); \
199 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
201 LL_HW_LOCK(xl);
207 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
209 LL_HW_UNLOCK(xl);
223 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
225 xl->agpSync = val;
226 xl->agpSyncTimeStamp = timeStamp;
232 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
234 if (xl->use_agp) {
235 viaBlit(xl, 32, xl->tsOffset, 1, xl->tsOffset, 1, 1, 1, 0, 0,
236 VIABLIT_FILL, xl->curTimeStamp);
237 return xl->curTimeStamp++;
243 viaDMAWaitTimeStamp(XvMCLowLevel * xl, CARD32 timeStamp, int doSleep)
249 if (xl->use_agp && (timeStamp > xl->lastReadTimeStamp)) {
256 while (timeStamp > (xl->lastReadTimeStamp = *xl->tsP)) {
259 if ((timeStamp > (xl->lastReadTimeStamp = *xl->tsP))) {
260 xl->errors |= LL_DMA_TIMEDOUT;
271 viaDMAInitTimeStamp(XvMCLowLevel * xl)
275 if (xl->use_agp) {
276 xl->tsMem.context = *(xl->drmcontext);
277 xl->tsMem.size = 64;
278 xl->tsMem.type = VIA_MEM_VIDEO;
279 if ((ret = drmCommandWriteRead(xl->fd, DRM_VIA_ALLOCMEM, &xl->tsMem,
280 sizeof(xl->tsMem))) < 0)
282 if (xl->tsMem.size != 64)
284 xl->tsOffset = (xl->tsMem.offset + 31) & ~31;
285 xl->tsP = (CARD32 *) xl->fbAddress + (xl->tsOffset >> 2);
286 xl->curTimeStamp = 1;
287 *xl->tsP = 0;
293 viaDMACleanupTimeStamp(XvMCLowLevel * xl)
296 if (!(xl->tsMem.size) || !xl->use_agp)
298 return drmCommandWrite(xl->fd, DRM_VIA_FREEMEM, &xl->tsMem,
299 sizeof(xl->tsMem));
303 viaMpegGetStatus(XvMCLowLevel * xl)
305 return MPEGIN(xl, 0x54);
309 viaMpegIsBusy(XvMCLowLevel * xl, CARD32 mask, CARD32 idle)
311 CARD32 tmp = viaMpegGetStatus(xl);
325 syncDMA(XvMCLowLevel * xl, unsigned int doSleep)
343 while (!(REGIN(xl, VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY)) {
346 if (!(REGIN(xl, VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY)) {
347 xl->errors |= LL_DMA_TIMEDOUT;
354 while (REGIN(xl, VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) {
357 if (REGIN(xl, VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) {
358 xl->errors |= LL_DMA_TIMEDOUT;
368 syncVideo(XvMCLowLevel * xl, unsigned int doSleep)
386 while (VIDIN(xl, HQV_CONTROL) & (HQV_SW_FLIP | HQV_SUBPIC_FLIP)) {
389 if (VIDIN(xl, HQV_CONTROL) & (HQV_SW_FLIP | HQV_SUBPIC_FLIP)) {
390 xl->errors |= LL_VIDEO_TIMEDOUT;
400 syncAccel(XvMCLowLevel * xl, unsigned int mode, unsigned int doSleep)
413 while (REGIN(xl, VIA_REG_STATUS) & mask) {
416 if (REGIN(xl, VIA_REG_STATUS) & mask) {
417 xl->errors |= LL_ACCEL_TIMEDOUT;
427 syncMpeg(XvMCLowLevel * xl, unsigned int mode, unsigned int doSleep)
455 while (viaMpegIsBusy(xl, busyMask, idleVal)) {
458 if (viaMpegIsBusy(xl, busyMask, idleVal)) {
459 xl->errors |= LL_DECODER_TIMEDOUT;
467 ret = viaMpegGetStatus(xl);
469 xl->errors |= ((ret & 0x70) >> 3);
475 pciFlush(XvMCLowLevel * xl)
479 unsigned mode = xl->curWaitFlags;
481 b.buf = (char *)xl->pci_buffer;
482 b.size = xl->pci_pos * sizeof(CARD32);
483 if (xl->performLocking)
484 hwlLock(xl, 0);
486 syncDMA(xl, 0);
488 syncAccel(xl, mode, 0);
490 syncVideo(xl, 0);
492 syncMpeg(xl, mode, 0);
493 ret = drmCommandWrite(xl->fd, DRM_VIA_PCICMD, &b, sizeof(b));
494 if (xl->performLocking)
495 hwlUnlock(xl, 0);
497 xl->errors |= LL_PCI_COMMAND_ERR;
499 xl->pci_pos = 0;
500 xl->curWaitFlags = 0;
504 agpFlush(XvMCLowLevel * xl)
509 if (xl->use_agp) {
510 b.buf = (char *)xl->agp_buffer;
511 b.size = xl->agp_pos * sizeof(CARD32);
512 if (xl->agpSync) {
513 syncXvMCLowLevel(xl, LL_MODE_DECODER_IDLE, 1,
514 xl->agpSyncTimeStamp);
515 xl->agpSync = 0;
517 if (xl->performLocking)
518 hwlLock(xl, 0);
520 ret = drmCommandWrite(xl->fd, DRM_VIA_CMDBUFFER, &b, sizeof(b));
522 if (xl->performLocking)
523 hwlUnlock(xl, 0);
526 xl->errors |= LL_AGP_COMMAND_ERR;
528 xl->agp_pos = 0;
530 xl->curWaitFlags &= LL_MODE_VIDEO;
532 unsigned mode = xl->curWaitFlags;
534 b.buf = (char *)xl->agp_buffer;
535 b.size = xl->agp_pos * sizeof(CARD32);
536 if (xl->performLocking)
537 hwlLock(xl, 0);
539 syncDMA(xl, 0);
541 syncAccel(xl, mode, 0);
543 syncVideo(xl, 0);
545 syncMpeg(xl, mode, 0);
546 ret = drmCommandWrite(xl->fd, DRM_VIA_PCICMD, &b, sizeof(b));
547 if (xl->performLocking)
548 hwlUnlock(xl, 0);
550 xl->errors |= LL_PCI_COMMAND_ERR;
552 xl->agp_pos = 0;
553 xl->curWaitFlags = 0;
561 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
563 if (xl->pci_pos)
564 pciFlush(xl);
565 if (xl->agp_pos)
566 agpFlush(xl);
567 errors = xl->errors;
568 xl->errors = 0;
575 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
577 if (xl->pci_pos)
578 pciFlush(xl);
579 if (!xl->use_agp && xl->agp_pos)
580 agpFlush(xl);
584 pciCommand(XvMCLowLevel * xl, unsigned offset, unsigned value, unsigned flags)
586 if (xl->pci_pos > (LL_PCI_CMDBUF_SIZE - 2))
587 pciFlush(xl);
589 xl->curWaitFlags |= flags;
590 xl->pci_buffer[xl->pci_pos++] = (offset >> 2) | 0xF0000000;
591 xl->pci_buffer[xl->pci_pos++] = value;
599 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
601 BEGIN_RING_AGP(xl, 2);
602 OUT_RING_QW_AGP(xl, H1_ADDR(0xc50),
604 WAITFLAGS(xl, LL_MODE_DECODER_IDLE);
611 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
613 pciCommand(xl, HQV_SRC_STARTADDR_Y, yOffs, LL_MODE_VIDEO);
614 pciCommand(xl, HQV_SRC_STARTADDR_U, uOffs, 0);
615 pciCommand(xl, HQV_SRC_STARTADDR_V, vOffs, 0);
622 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
651 pciCommand(xl, HQV_CONTROL, (VIDIN(xl,
659 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
662 BEGIN_RING_AGP(xl, 6);
663 OUT_RING_QW_AGP(xl, H1_ADDR(0xc20 + i), yOffs >> 3);
664 OUT_RING_QW_AGP(xl, H1_ADDR(0xc24 + i), uOffs >> 3);
665 OUT_RING_QW_AGP(xl, H1_ADDR(0xc28 + i), vOffs >> 3);
666 WAITFLAGS(xl, LL_MODE_DECODER_IDLE);
675 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
684 BEGIN_RING_AGP(xl, 144);
685 WAITFLAGS(xl, LL_MODE_DECODER_IDLE);
687 OUT_RING_QW_AGP(xl, H1_ADDR(0xc00),
693 OUT_RING_QW_AGP(xl, H1_ADDR(0xc5c), 0);
695 OUT_RING_QW_AGP(xl, H1_ADDR(0xc60),
705 OUT_RING_QW_AGP(xl, H1_ADDR(0xc5c), 1);
707 OUT_RING_QW_AGP(xl, H1_ADDR(0xc60),
717 OUT_RING_QW_AGP(xl, H1_ADDR(0xc5c), 2);
719 OUT_RING_QW_AGP(xl, H1_ADDR(0xc60),
729 OUT_RING_QW_AGP(xl, H1_ADDR(0xc5c), 3);
731 OUT_RING_QW_AGP(xl, H1_ADDR(0xc60),
740 OUT_RING_QW_AGP(xl, H1_ADDR(0xc90),
747 OUT_RING_QW_AGP(xl, H1_ADDR(0xc94),
754 OUT_RING_QW_AGP(xl, H1_ADDR(0xc98),
768 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
770 BEGIN_RING_AGP(xl, 100);
771 WAITFLAGS(xl, LL_MODE_DECODER_IDLE);
774 OUT_RING_QW_AGP(xl, H1_ADDR(0xc08), 0);
776 OUT_RING_QW_AGP(xl, H1_ADDR(0xc98), 0x400000);
779 OUT_RING_QW_AGP(xl, H1_ADDR(0xc0c), 0x43 | 0x20);
781 OUT_RING_QW_AGP(xl, H1_ADDR(j), 0);
784 OUT_RING_QW_AGP(xl, H1_ADDR(0xc0c), 0xc3 | 0x20);
786 OUT_RING_QW_AGP(xl, H1_ADDR(j), 0);
796 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
798 if (xl->errors & (LL_DECODER_TIMEDOUT |
813 BEGIN_RING_AGP(xl, 4);
814 WAITFLAGS(xl, LL_MODE_DECODER_IDLE);
816 OUT_RING_QW_AGP(xl, H1_ADDR(0xc9c), nBytes);
819 OUT_RING_QW_AGP(xl, H1_ADDR(0xca0), sCode);
827 BEGIN_RING_AGP(xl, (count - i) << 1);
830 OUT_RING_QW_AGP(xl, H1_ADDR(0xca0), *buf++);
834 BEGIN_RING_AGP(xl, 6);
837 OUT_RING_QW_AGP(xl, H1_ADDR(0xca0), *buf & ((1 << (r << 3)) - 1));
839 OUT_RING_QW_AGP(xl, H1_ADDR(0xca0), 0);
840 OUT_RING_QW_AGP(xl, H1_ADDR(0xca0), 0);
849 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
851 stride = VIDIN(xl, SUBP_CONTROL_STRIDE);
853 pciCommand(xl, SUBP_CONTROL_STRIDE, stride & ~SUBP_HQV_ENABLE,
863 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
866 pciCommand(xl, RAM_TABLE_CONTROL, pViaSubPic->palette[i],
870 pciCommand(xl, SUBP_STARTADDR, pViaSubPic->offset, 0);
873 pciCommand(xl, SUBP_CONTROL_STRIDE, cWord, 0);
885 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
920 BEGIN_RING_AGP(xl, 20);
921 WAITFLAGS(xl, LL_MODE_2D);
923 OUT_RING_QW_AGP(xl, H1_ADDR(VIA_REG_GEMODE), dwGEMode);
939 OUT_RING_QW_AGP(xl, H1_ADDR(VIA_REG_SRCCOLORKEY), color);
940 OUT_RING_QW_AGP(xl, H1_ADDR(VIA_REG_KEYCONTROL), 0x4000);
944 OUT_RING_QW_AGP(xl, H1_ADDR(VIA_REG_FGCOLOR), color);
948 OUT_RING_QW_AGP(xl, H1_ADDR(VIA_REG_KEYCONTROL), 0x0);
952 OUT_RING_QW_AGP(xl, H1_ADDR(VIA_REG_SRCBASE), (srcBase & ~31) >> 3);
953 OUT_RING_QW_AGP(xl, H1_ADDR(VIA_REG_DSTBASE), (dstBase & ~31) >> 3);
954 OUT_RING_QW_AGP(xl, H1_ADDR(VIA_REG_PITCH), VIA_PITCH_ENABLE |
956 OUT_RING_QW_AGP(xl, H1_ADDR(VIA_REG_SRCPOS), ((srcY << 16) | srcX));
957 OUT_RING_QW_AGP(xl, H1_ADDR(VIA_REG_DSTPOS), ((dstY << 16) | dstX));
958 OUT_RING_QW_AGP(xl, H1_ADDR(VIA_REG_DIMENSION),
960 OUT_RING_QW_AGP(xl, H1_ADDR(VIA_REG_GECMD), cmd);
968 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
971 errors = xl->errors;
972 xl->errors = 0;
976 if ((mode & (LL_MODE_VIDEO | LL_MODE_3D)) || !xl->use_agp) {
977 if (xl->performLocking)
978 hwlLock(xl, 0);
980 syncDMA(xl, doSleep);
982 syncAccel(xl, mode, doSleep);
984 syncVideo(xl, doSleep);
985 if (xl->performLocking)
986 hwlUnlock(xl, 0);
988 viaDMAWaitTimeStamp(xl, timeStamp, doSleep);
992 syncMpeg(xl, mode, doSleep);
994 errors = xl->errors;
995 xl->errors = 0;
1007 XvMCLowLevel *xl;
1015 xl = (XvMCLowLevel *) malloc(sizeof(XvMCLowLevel));
1017 if (!xl)
1020 xl->agp_pos = 0;
1021 xl->pci_pos = 0;
1022 xl->use_agp = useAgp;
1023 xl->fd = fd;
1024 xl->drmcontext = ctx;
1025 xl->hwLock = hwLock;
1026 xl->mmioAddress = mmioAddress;
1027 xl->fbAddress = fbAddress;
1028 xl->curWaitFlags = 0;
1029 xl->performLocking = 1;
1030 xl->errors = 0;
1031 xl->agpSync = 0;
1032 ret = viaDMAInitTimeStamp(xl);
1034 free(xl);
1037 return xl;
1043 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
1045 xl->performLocking = performLocking;
1051 XvMCLowLevel *xl = (XvMCLowLevel *) xlp;
1053 viaDMACleanupTimeStamp(xl);
1054 free(xl);