Cross Reference: /xsrc/external/mit/xf86-video-rendition/dist/src/v1krisc.c

Lines Matching defs:io_base
89 static vu32 readRF(unsigned long io_base, vu8 index);
90 static void writeRF(unsigned long io_base, vu8 index, vu32 data);
92 static vu32 risc_readmem(unsigned long io_base, vu32 addr, vu8 read_type);
93 static void risc_writemem(unsigned long io_base, vu32 addr, vu32 data, vu8 write_type);
96 static void risc_step(unsigned long io_base, vu32 count);
98 static void risc_forcestep(unsigned long io_base, vu32 instruction);
99 static void risc_continue(unsigned long io_base);
116   unsigned long io_base=pRendition->board.io_base;
119   risc_forcestep(io_base, NOP_INSTR);
120   risc_forcestep(io_base, NOP_INSTR);
121   risc_forcestep(io_base, NOP_INSTR);
122   risc_forcestep(io_base, JMP_INSTR(JMP_OP, pc>>2));
123   risc_forcestep(io_base, NOP_INSTR);
140   risc_continue(pRendition->board.io_base);
155   unsigned long io_base=pRendition->board.io_base;
159   debugreg=verite_in8(io_base+DEBUGREG);
164 /*      if(!(c%10000))ErrorF("#S1# !0x%x! -- ",verite_in8(io_base+STATUS)); */
165       statusreg = verite_in8(io_base+STATUS);
173     verite_out8(io_base+DEBUGREG, debugreg|HOLDRISC);
178 /*	if(!(c%10000))ErrorF("#S2# !0x%x! -- ",verite_in8(io_base+STATUS)); */
179 	statusreg = verite_in8(io_base+STATUS);
189     verite_out8(io_base+DEBUGREG, debugreg|HOLDRISC);
191     verite_iopoll(io_base+STATEDATA, 0, 0); /* short pause */
192     verite_iopoll(io_base+STATEDATA, 0, 0); /* short pause */
193     verite_iopoll(io_base+STATEDATA, 0, 0); /* short pause */
210   unsigned long io_base=pRendition->board.io_base;
213   p1=risc_readmem(io_base, 0, READ_WORD);
214   p2=risc_readmem(io_base, 8, READ_WORD);
215   risc_writemem(io_base, 0, p1, WRITE_WORD);
216   risc_writemem(io_base, 8, p2, WRITE_WORD);
217   (void)risc_readmem(io_base, 0, READ_WORD);
218   (void)risc_readmem(io_base, 8, READ_WORD);
222   risc_forcestep(io_base, INT_INSTR(SPRI_OP, 0, 0, 31)); /* spri Sync,zero */
223   risc_forcestep(io_base, NOP_INSTR);
224   risc_forcestep(io_base, NOP_INSTR);
225   risc_forcestep(io_base, NOP_INSTR);
228   writeRF(io_base, RISC_RA, ICACHE_ONOFF_MASK);        /* load mask */
230   risc_forcestep(io_base, INT_INSTR(OR_OP, RISC_FLAG, RISC_FLAG, RISC_RA));
231   risc_forcestep(io_base, NOP_INSTR);                  /* clear hazard */
232   risc_forcestep(io_base, NOP_INSTR);
233   risc_forcestep(io_base, NOP_INSTR);
237     risc_forcestep(io_base, JMP_INSTR(JMP_OP, c>>2)); /* jmp NextCacheLine. */
239   writeRF(io_base, RISC_RA, ICACHE_ONOFF_MASK);      /* load mask */
241   risc_forcestep(io_base, INT_INSTR(ANDN_OP, RISC_FLAG, RISC_FLAG, RISC_RA));
242   risc_forcestep(io_base, NOP_INSTR);                /* jump back to PC=0 */
243   risc_forcestep(io_base, JMP_INSTR(JMP_OP, 0));
244   risc_forcestep(io_base, NOP_INSTR);
258   unsigned long io_base=pRendition->board.io_base;
260   verite_out8(io_base+DEBUGREG, SOFTRESET|HOLDRISC);
261   verite_out8(io_base+STATEINDEX, STATEINDEX_PC);
262   verite_iopoll(io_base+STATEDATA, 0, 0xffffffff);
263   verite_iopoll(io_base+STATEDATA, 0, 0xffffffff);
264   verite_iopoll(io_base+STATEDATA, 0, 0xffffffff);
266   verite_out8(io_base+DEBUGREG, HOLDRISC);
267   verite_iopoll(io_base+STATEDATA, 0, 0);
268   verite_iopoll(io_base+STATEDATA, 0, 0);
269   verite_iopoll(io_base+STATEDATA, 0, 0);
272   risc_forcestep(io_base, LI_INSTR(LI_OP, RISC_RA, ICACHE_ONOFF_MASK&0xffff));
273   risc_forcestep(io_base, INT_INSTR(ADDIFI_OP, RISC_FLAG, RISC_RA, 
276   verite_out8(io_base+INTR, 0xff);
278   verite_out8(io_base+MEMENDIAN, MEMENDIAN_NO);	
343  * static vu32 readRF(unsigned long io_base, vu8 index)
348 readRF(unsigned long io_base, vu8 index)
353   debug=verite_in8(io_base+DEBUGREG);
354   stateindex=verite_in8(io_base+STATEINDEX);
359   verite_out8(io_base+DEBUGREG, debug|HOLDRISC);
362   verite_out32(io_base+STATEDATA, instr);
365   verite_out8(io_base+STATEINDEX, STATEINDEX_IR);  /* point at DEC_IR */
366   verite_iopoll(io_base+STATEDATA, instr, 0xffffffff);
368   verite_out8(io_base+STATEINDEX, STATEINDEX_S1);  /* point at RISCS1 */
369   verite_iopoll(io_base+STATEINDEX, 0, 0);         /* short pause */
370   data=verite_in32(io_base+STATEDATA);             /* read RF */
372   verite_out8(io_base+STATEINDEX, stateindex);     /* restore state_index */
373   verite_out8(io_base+DEBUGREG, debug);            /* restore debug */
381  * static void writeRF(unsigned long io_base, vu8 index, vu32 data)
386 writeRF(unsigned long io_base, vu8 index, vu32 data)
397 	risc_forcestep(io_base, LI_INSTR(LI_OP,index,data&0xffff));
399 	  risc_forcestep(io_base, INT_INSTR(ADDIFI_OP,index,index,data>>16) );
402 	risc_forcestep(io_base, LI_INSTR(LUI_OP, index, data>>16));
403 	risc_forcestep(io_base, INT_INSTR(ADDSL8_OP, index, index, (data>>8)&0xff));
404 	risc_forcestep(io_base, INT_INSTR(ADDI_OP, index, index, data&0xff));
409 	risc_forcestep(io_base, INT_INSTR(ADD_OP, special, 0, RISC_SP));
411     risc_forcestep(io_base, NOP_INSTR);	
412 	risc_forcestep(io_base, NOP_INSTR);
413 	risc_forcestep(io_base, NOP_INSTR);
420  * static vu32 risc_readmem(unsigned long io_base, vu32 addr, vu8 read_type)
425 risc_readmem(unsigned long io_base, vu32 addr, vu8 read_type)
429   writeRF(io_base, RISC_RA, addr);          /* point to memory */
431 	risc_forcestep(io_base, LD_INSTR(LB_OP, RISC_SP, 0, RISC_RA));
434 	  risc_forcestep(io_base, LD_INSTR(LH_OP, RISC_SP, 0, RISC_RA));
436 	  risc_forcestep(io_base, LD_INSTR(LW_OP, RISC_SP, 0, RISC_RA));
438   risc_forcestep(io_base, NOP_INSTR);      /* need nop's */
439   risc_forcestep(io_base, NOP_INSTR);      /* need nop's */
440   data=readRF(io_base, RISC_SP);           /* get data */
448  * static vu32 risc_writemem(unsigned long io_base, vu32 addr, vu32 data, vu8 write_type)
453 risc_writemem(unsigned long io_base, vu32 addr, vu32 data, vu8 write_type)
455   writeRF(io_base, RISC_RA, addr);          /* point to memory */
456   writeRF(io_base, RISC_FP, data);          /* set data */
458     risc_forcestep(io_base, STR_INSTR(SB_OP, 0, RISC_FP, RISC_RA));
461       risc_forcestep(io_base, STR_INSTR(SH_OP, 0, RISC_FP, RISC_RA));
463       risc_forcestep(io_base, STR_INSTR(SW_OP, 0, RISC_FP, RISC_RA));
469  * static void risc_step(unsigned long io_base, vu32 count)
474 risc_step(unsigned long io_base, vu32 count)
482     debugreg=verite_in8(io_base+DEBUGREG);
483     verite_out8(io_base+DEBUGREG, debugreg|STEPRISC); 
486       if(0 == (verite_in8(io_base+DEBUGREG)&STEPRISC))
497  * static void risc_forcestep(unsigned long io_base, vu32 instruction)
502 risc_forcestep(unsigned long io_base, vu32 instruction)
508   debugreg=verite_in8(io_base+DEBUGREG);
509   stateindex=verite_in8(io_base+STATEINDEX);
510   verite_out8(io_base+STATEINDEX, STATEINDEX_IR);
511   verite_iopoll8(io_base+STATEINDEX, STATEINDEX_IR, 0xff);    /* wait */
512   verite_out32(io_base+STATEDATA, instruction);               /* load instruction */
513   verite_iopoll(io_base+STATEDATA, instruction, 0xffffffff);  /* wait */
514   verite_out8(io_base+DEBUGREG, debugreg|HOLDRISC|STEPRISC);  /* step */
515   verite_iopoll(io_base+STATEDATA, 0, 0);                     /* short pause */
518     if (HOLDRISC == (verite_in8(io_base+DEBUGREG) & (HOLDRISC|STEPRISC)))
522   verite_out8(io_base+STATEINDEX, stateindex);
528  * static void risc_continue(unsigned long io_base)
533 risc_continue(unsigned long io_base)
537   debugreg=verite_in8(io_base+DEBUGREG);
538   verite_out8(io_base+DEBUGREG, debugreg&(~HOLDRISC));
539   verite_iopoll(io_base+STATEDATA, 0, 0);    /* short pause */