Lines Matching defs:pSmi
56 static void SMI501_SetClock(SMIPtr pSmi, int32_t port,
67 SMIPtr pSmi = SMIPTR(pScrn);
68 MSOCRegPtr save = pSmi->save;
75 save->system_ctl.value = READ_SCR(pSmi, SYSTEM_CTL);
78 save->misc_ctl.value = READ_SCR(pSmi, MISC_CTL);
81 save->power_ctl.value = READ_SCR(pSmi, POWER_CTL);
103 save->gate.value = READ_SCR(pSmi, save->current_gate);
104 save->clock.value = READ_SCR(pSmi, save->current_clock);
107 save->timing_ctl.value = READ_SCR(pSmi, TIMING_CTL);
109 save->pll_ctl.value = READ_SCR(pSmi, PLL_CTL);
110 save->device_id.value = READ_SCR(pSmi, DEVICE_ID);
111 save->sleep_gate.value = READ_SCR(pSmi, SLEEP_GATE);
113 save->panel_display_ctl.value = READ_SCR(pSmi, PANEL_DISPLAY_CTL);
114 save->panel_fb_address.value = READ_SCR(pSmi, PANEL_FB_ADDRESS);
115 save->panel_fb_width.value = READ_SCR(pSmi, PANEL_FB_WIDTH);
116 save->panel_wwidth.value = READ_SCR(pSmi, PANEL_WWIDTH);
117 save->panel_wheight.value = READ_SCR(pSmi, PANEL_WHEIGHT);
118 save->panel_plane_tl.value = READ_SCR(pSmi, PANEL_PLANE_TL);
119 save->panel_plane_br.value = READ_SCR(pSmi, PANEL_PLANE_BR);
120 save->panel_htotal.value = READ_SCR(pSmi, PANEL_HTOTAL);
121 save->panel_hsync.value = READ_SCR(pSmi, PANEL_HSYNC);
122 save->panel_vtotal.value = READ_SCR(pSmi, PANEL_VTOTAL);
123 save->panel_vsync.value = READ_SCR(pSmi, PANEL_VSYNC);
125 save->crt_display_ctl.value = READ_SCR(pSmi, CRT_DISPLAY_CTL);
126 save->crt_fb_address.value = READ_SCR(pSmi, CRT_FB_ADDRESS);
127 save->crt_fb_width.value = READ_SCR(pSmi, CRT_FB_WIDTH);
128 save->crt_htotal.value = READ_SCR(pSmi, CRT_HTOTAL);
129 save->crt_hsync.value = READ_SCR(pSmi, CRT_HSYNC);
130 save->crt_vtotal.value = READ_SCR(pSmi, CRT_VTOTAL);
131 save->crt_vsync.value = READ_SCR(pSmi, CRT_VSYNC);
133 save->alpha_display_ctl.value = READ_SCR(pSmi, ALPHA_DISPLAY_CTL);
134 save->alpha_fb_address.value = READ_SCR(pSmi, ALPHA_FB_ADDRESS);
135 save->alpha_fb_width.value = READ_SCR(pSmi, ALPHA_FB_WIDTH);
136 save->alpha_plane_tl.value = READ_SCR(pSmi, ALPHA_PLANE_TL);
137 save->alpha_plane_br.value = READ_SCR(pSmi, ALPHA_PLANE_BR);
138 save->alpha_chroma_key.value = READ_SCR(pSmi, ALPHA_CHROMA_KEY);
141 save->accel_src = READ_SCR(pSmi, ACCEL_SRC);
142 save->accel_dst = READ_SCR(pSmi, ACCEL_DST);
143 save->accel_dim = READ_SCR(pSmi, ACCEL_DIM);
144 save->accel_ctl = READ_SCR(pSmi, ACCEL_CTL);
145 save->accel_pitch = READ_SCR(pSmi, ACCEL_PITCH);
146 save->accel_fmt = READ_SCR(pSmi, ACCEL_FMT);
147 save->accel_clip_tl = READ_SCR(pSmi, ACCEL_CLIP_TL);
148 save->accel_clip_br = READ_SCR(pSmi, ACCEL_CLIP_BR);
149 save->accel_pat_lo = READ_SCR(pSmi, ACCEL_PAT_LO);
150 save->accel_pat_hi = READ_SCR(pSmi, ACCEL_PAT_HI);
151 save->accel_wwidth = READ_SCR(pSmi, ACCEL_WWIDTH);
152 save->accel_src_base = READ_SCR(pSmi, ACCEL_SRC_BASE);
153 save->accel_dst_base = READ_SCR(pSmi, ACCEL_DST_BASE);
160 SMIPtr pSmi = SMIPTR(pScrn);
162 if (pSmi->CurrentDPMS != PowerManagementMode) {
166 pSmi->CurrentDPMS = PowerManagementMode;
175 SMIPtr pSmi = SMIPTR(pScrn);
178 save = pSmi->save;
179 mode = pSmi->mode;
184 if (pSmi->UseFBDev)
203 if (pSmi->MCLK) {
205 "MCLK request %d\n", pSmi->MCLK);
206 (void)SMI501_FindMemClock(pSmi->MCLK, &x_select, &x_divider, &x_shift);
213 if (pSmi->MXCLK) {
215 "MXCLK request %d\n", pSmi->MXCLK);
216 (void)SMI501_FindMemClock(pSmi->MXCLK, &x_select, &x_divider, &x_shift);
223 if (!pSmi->Dualhead) {
241 SMIPtr pSmi = SMIPTR(pScrn);
243 if (!pSmi->UseFBDev) {
245 WRITE_SCR(pSmi, mode->current_gate, mode->gate.value);
247 clock.value = READ_SCR(pSmi, mode->current_clock);
249 if (pSmi->MCLK) {
254 SMI501_SetClock(pSmi, mode->current_clock, pll, clock.value);
257 if (pSmi->MXCLK) {
262 SMI501_SetClock(pSmi, mode->current_clock, pll, clock.value);
265 WRITE_SCR(pSmi, MISC_CTL, mode->misc_ctl.value);
267 WRITE_SCR(pSmi, POWER_CTL, mode->power_ctl.value);
275 pSmi->PCIBurst != FALSE;
276 mode->system_ctl.f.retry = pSmi->PCIRetry != FALSE;
277 WRITE_SCR(pSmi, SYSTEM_CTL, mode->system_ctl.value);
279 if (!pSmi->Dualhead)
280 WRITE_SCR(pSmi, CRT_DISPLAY_CTL, mode->crt_display_ctl.value);
288 SMIPtr pSmi = SMIPTR(pScrn);
290 if (!pSmi->UseFBDev) {
291 clock.value = READ_SCR(pSmi, mode->current_clock);
296 WRITE_SCR(pSmi, PLL_CTL, mode->pll_ctl.value);
303 SMI501_SetClock(pSmi, mode->current_clock, pll, clock.value);
305 WRITE_SCR(pSmi, PANEL_FB_ADDRESS, mode->panel_fb_address.value);
306 WRITE_SCR(pSmi, PANEL_FB_WIDTH, mode->panel_fb_width.value);
308 WRITE_SCR(pSmi, PANEL_WWIDTH, mode->panel_wwidth.value);
309 WRITE_SCR(pSmi, PANEL_WHEIGHT, mode->panel_wheight.value);
311 WRITE_SCR(pSmi, PANEL_PLANE_TL, mode->panel_plane_tl.value);
312 WRITE_SCR(pSmi, PANEL_PLANE_BR, mode->panel_plane_br.value);
314 WRITE_SCR(pSmi, PANEL_HTOTAL, mode->panel_htotal.value);
315 WRITE_SCR(pSmi, PANEL_HSYNC, mode->panel_hsync.value);
316 WRITE_SCR(pSmi, PANEL_VTOTAL, mode->panel_vtotal.value);
317 WRITE_SCR(pSmi, PANEL_VSYNC, mode->panel_vsync.value);
318 WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value);
327 SMIPtr pSmi = SMIPTR(pScrn);
329 if (!pSmi->UseFBDev) {
330 clock.value = READ_SCR(pSmi, mode->current_clock);
337 SMI501_SetClock(pSmi, mode->current_clock, pll, clock.value);
339 WRITE_SCR(pSmi, CRT_FB_ADDRESS, mode->crt_fb_address.value);
340 WRITE_SCR(pSmi, CRT_FB_WIDTH, mode->crt_fb_width.value);
341 WRITE_SCR(pSmi, CRT_HTOTAL, mode->crt_htotal.value);
342 WRITE_SCR(pSmi, CRT_HSYNC, mode->crt_hsync.value);
343 WRITE_SCR(pSmi, CRT_VTOTAL, mode->crt_vtotal.value);
344 WRITE_SCR(pSmi, CRT_VSYNC, mode->crt_vsync.value);
345 WRITE_SCR(pSmi, CRT_DISPLAY_CTL, mode->crt_display_ctl.value);
352 SMIPtr pSmi = SMIPTR(pScrn);
354 WRITE_SCR(pSmi, ALPHA_FB_ADDRESS, mode->alpha_fb_address.value);
355 WRITE_SCR(pSmi, ALPHA_FB_WIDTH, mode->alpha_fb_width.value);
357 WRITE_SCR(pSmi, ALPHA_PLANE_TL, mode->alpha_plane_tl.value);
358 WRITE_SCR(pSmi, ALPHA_PLANE_BR, mode->alpha_plane_br.value);
360 WRITE_SCR(pSmi, ALPHA_CHROMA_KEY, mode->alpha_chroma_key.value);
362 WRITE_SCR(pSmi, ALPHA_DISPLAY_CTL, mode->alpha_display_ctl.value);
368 SMIPtr pSmi = SMIPTR(pScrn);
378 WRITE_SCR(pSmi, ACCEL_SRC, restore->accel_src);
379 WRITE_SCR(pSmi, ACCEL_DST, restore->accel_dst);
380 WRITE_SCR(pSmi, ACCEL_DIM, restore->accel_dim);
381 WRITE_SCR(pSmi, ACCEL_CTL, restore->accel_ctl);
382 WRITE_SCR(pSmi, ACCEL_PITCH, restore->accel_pitch);
383 WRITE_SCR(pSmi, ACCEL_FMT, restore->accel_fmt);
384 WRITE_SCR(pSmi, ACCEL_CLIP_TL, restore->accel_clip_tl);
385 WRITE_SCR(pSmi, ACCEL_CLIP_BR, restore->accel_clip_br);
386 WRITE_SCR(pSmi, ACCEL_PAT_LO, restore->accel_pat_lo);
387 WRITE_SCR(pSmi, ACCEL_PAT_HI, restore->accel_pat_hi);
388 WRITE_SCR(pSmi, ACCEL_WWIDTH, restore->accel_wwidth);
389 WRITE_SCR(pSmi, ACCEL_SRC_BASE, restore->accel_src_base);
390 WRITE_SCR(pSmi, ACCEL_DST_BASE, restore->accel_dst_base);
396 SMIPtr pSmi = SMIPTR(pScrn);
400 WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value);
401 SMI501_WaitVSync(pSmi, 4);
404 WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value);
405 SMI501_WaitVSync(pSmi, 4);
408 WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value);
409 SMI501_WaitVSync(pSmi, 4);
412 WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value);
413 SMI501_WaitVSync(pSmi, 4);
417 WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value);
418 SMI501_WaitVSync(pSmi, 4);
421 WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value);
422 SMI501_WaitVSync(pSmi, 4);
425 WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value);
426 SMI501_WaitVSync(pSmi, 4);
429 WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value);
430 SMI501_WaitVSync(pSmi, 4);
598 SMIPtr pSmi = SMIPTR(pScrn);
603 format_integer_base2(READ_SCR(pSmi, i)));
607 format_integer_base2(READ_SCR(pSmi, i)));
611 SMI501_WaitVSync(SMIPtr pSmi, int vsync_count)
621 status.value = READ_SCR(pSmi, CMD_STATUS);
629 status.value = READ_SCR(pSmi, CMD_STATUS);
637 SMI501_SetClock(SMIPtr pSmi, int32_t port, int32_t pll, int32_t value)
661 WRITE_SCR(pSmi, port, pll);
662 SMI501_WaitVSync(pSmi, 1);
665 WRITE_SCR(pSmi, port, value);
666 SMI501_WaitVSync(pSmi, 1);