Lines Matching refs:vclk
187 unsigned int vclk[5];
510 SiSCalcClock(pScrn, clock, 2, vclk);
518 pReg->sisRegs3C4[0x2A] = (vclk[Midx] - 1) & 0x7f;
519 pReg->sisRegs3C4[0x2A] |= ((vclk[VLDidx] == 2) ? 1 : 0) << 7;
522 pReg->sisRegs3C4[0x2B] = (vclk[Nidx] - 1) & 0x1f;
524 if(vclk[Pidx] <= 4){
526 pReg->sisRegs3C4[0x2B] |= (vclk[Pidx] - 1) << 5;
530 pReg->sisRegs3C4[0x2B] |= ((vclk[Pidx] / 2) - 1) << 5;
646 SiSCalcClock(pScrn, pSiS->MemClock, 1, vclk);
648 pReg->sisRegs3C4[0x28] = (vclk[Midx] - 1) & 0x7f ;
649 pReg->sisRegs3C4[0x28] |= ((vclk[VLDidx] == 2 ) ? 1 : 0 ) << 7 ;
650 pReg->sisRegs3C4[0x29] = (vclk[Nidx] -1) & 0x1f ; /* bits [4:0] contain denumerator -MC */
651 if(vclk[Pidx] <= 4) {
652 pReg->sisRegs3C4[0x29] |= (vclk[Pidx] - 1) << 5 ; /* postscale 1,2,3,4 */
655 pReg->sisRegs3C4[0x29] |= ((vclk[Pidx] / 2) - 1) << 5 ; /* postscale 6,8 */