Lines Matching defs:dac
2 * Acceleration for the Creator and Creator3D framebuffer - DAC programming.
52 ffb_dacPtr dac = pFfb->dac;
61 DACCUR_WRITE(dac, FFBDAC_CUR_POS, posval);
67 ffb_dacPtr dac = pFfb->dac;
69 dac->cur = FFBDAC_CUR_COLOR1;
70 dac->curdata = bg;
71 dac->curdata = fg;
78 ffb_dacPtr dac = pFfb->dac;
91 DACCUR_WRITE(dac, FFBDAC_CUR_CTRL, val);
97 ffb_dacPtr dac = pFfb->dac;
100 dac->cur = FFBDAC_CUR_BITMAP_P0;
105 dac->curdata = *bitmap++;
108 dac->curdata = (bitmap[0] << xshift) |
110 dac->curdata = bitmap[1] << xshift;
114 dac->curdata = bitmap[1] << (xshift - 32);
115 dac->curdata = 0;
120 dac->curdata = 0;
133 ffb_dacPtr dac = pFfb->dac;
172 dac->cfg = FFBDAC_CFG_CLUP(palette) + index;
173 dac->cfgdata = regval;
181 ffb_dacPtr dac = pFfb->dac;
184 tgctrl = DACCFG_READ(dac, FFBDAC_CFG_TGEN);
197 unsigned int vctr = DACCFG_READ(dac, FFBDAC_CFG_TGVC);
203 DACCFG_WRITE(dac, FFBDAC_CFG_TGEN, 0);
208 * between several operations. We have to stop the DAC while
220 ffb_dacPtr dac = pFfb->dac;
229 DACCFG_WRITE(dac, FFBDAC_CFG_VBNP, state->vbnp);
230 DACCFG_WRITE(dac, FFBDAC_CFG_VBAP, state->vbap);
231 DACCFG_WRITE(dac, FFBDAC_CFG_VSNP, state->vsnp);
232 DACCFG_WRITE(dac, FFBDAC_CFG_VSAP, state->vsap);
233 DACCFG_WRITE(dac, FFBDAC_CFG_HSNP, state->hsnp);
234 DACCFG_WRITE(dac, FFBDAC_CFG_HBNP, state->hbnp);
235 DACCFG_WRITE(dac, FFBDAC_CFG_HBAP, state->hbap);
236 DACCFG_WRITE(dac, FFBDAC_CFG_HSYNCNP, state->hsyncnp);
237 DACCFG_WRITE(dac, FFBDAC_CFG_HSYNCAP, state->hsyncap);
238 DACCFG_WRITE(dac, FFBDAC_CFG_HSCENNP, state->hscennp);
239 DACCFG_WRITE(dac, FFBDAC_CFG_HSCENAP, state->hscenap);
240 DACCFG_WRITE(dac, FFBDAC_CFG_EPNP, state->epnp);
241 DACCFG_WRITE(dac, FFBDAC_CFG_EINP, state->einp);
242 DACCFG_WRITE(dac, FFBDAC_CFG_EIAP, state->eiap);
244 /* Step 3: Restore rest of DAC hw state. */
245 DACCFG_WRITE(dac, FFBDAC_CFG_PPLLCTRL, state->ppllctrl);
246 DACCFG_WRITE(dac, FFBDAC_CFG_GPLLCTRL, state->gpllctrl);
247 DACCFG_WRITE(dac, FFBDAC_CFG_PFCTRL, state->pfctrl);
248 DACCFG_WRITE(dac, FFBDAC_CFG_UCTRL, state->uctrl);
251 dac->cfg = FFBDAC_CFG_CLUP_BASE;
253 dac->cfgdata = state->clut[i];
256 dac->cfg = FFBDAC_PAC2_AOVWLUT0;
258 dac->cfgdata = state->ovluts[i];
261 DACCFG_WRITE(dac, FFBDAC_CFG_WTCTRL, state->wtctrl);
262 DACCFG_WRITE(dac, FFBDAC_CFG_TMCTRL, state->tmctrl);
263 DACCFG_WRITE(dac, FFBDAC_CFG_TCOLORKEY, state->tcolorkey);
265 DACCFG_WRITE(dac, FFBDAC_CFG_WAMASK, state->wamask);
268 dac->cfg = FFBDAC_PAC1_APWLUT_BASE;
270 dac->cfgdata = state->pwluts[i];
272 dac->cfg = FFBDAC_PAC2_APWLUT_BASE;
274 dac->cfgdata = state->pwluts[i];
277 DACCFG_WRITE(dac, FFBDAC_CFG_DACCTRL, state->dacctrl);
289 DACCFG_WRITE(dac, FFBDAC_CFG_TGEN, state->tgen);
293 (void) DACCFG_READ(dac, FFBDAC_CFG_TGVC);
300 ffb_dacPtr dac = pFfb->dac;
303 state->ppllctrl = DACCFG_READ(dac, FFBDAC_CFG_PPLLCTRL);
304 state->gpllctrl = DACCFG_READ(dac, FFBDAC_CFG_GPLLCTRL);
305 state->pfctrl = DACCFG_READ(dac, FFBDAC_CFG_PFCTRL);
306 state->uctrl = DACCFG_READ(dac, FFBDAC_CFG_UCTRL);
309 dac->cfg = FFBDAC_CFG_CLUP_BASE;
311 state->clut[i] = dac->cfgdata;
314 dac->cfg = FFBDAC_PAC2_AOVWLUT0;
316 state->ovluts[i] = dac->cfgdata;
319 state->wtctrl = DACCFG_READ(dac, FFBDAC_CFG_WTCTRL);
320 state->tmctrl = DACCFG_READ(dac, FFBDAC_CFG_TMCTRL);
321 state->tcolorkey = DACCFG_READ(dac, FFBDAC_CFG_TCOLORKEY);
323 state->wamask = DACCFG_READ(dac, FFBDAC_CFG_WAMASK);
326 dac->cfg = FFBDAC_PAC1_APWLUT_BASE;
328 state->pwluts[i] = dac->cfgdata;
330 dac->cfg = FFBDAC_PAC2_APWLUT_BASE;
332 state->pwluts[i] = dac->cfgdata;
335 state->dacctrl = DACCFG_READ(dac, FFBDAC_CFG_DACCTRL);
337 state->tgen = DACCFG_READ(dac, FFBDAC_CFG_TGEN);
338 state->vbnp = DACCFG_READ(dac, FFBDAC_CFG_VBNP);
339 state->vbap = DACCFG_READ(dac, FFBDAC_CFG_VBAP);
340 state->vsnp = DACCFG_READ(dac, FFBDAC_CFG_VSNP);
341 state->vsap = DACCFG_READ(dac, FFBDAC_CFG_VSAP);
342 state->hsnp = DACCFG_READ(dac, FFBDAC_CFG_HSNP);
343 state->hbnp = DACCFG_READ(dac, FFBDAC_CFG_HBNP);
344 state->hbap = DACCFG_READ(dac, FFBDAC_CFG_HBAP);
345 state->hsyncnp = DACCFG_READ(dac, FFBDAC_CFG_HSYNCNP);
346 state->hsyncap = DACCFG_READ(dac, FFBDAC_CFG_HSYNCAP);
347 state->hscennp = DACCFG_READ(dac, FFBDAC_CFG_HSCENNP);
348 state->hscenap = DACCFG_READ(dac, FFBDAC_CFG_HSCENAP);
349 state->epnp = DACCFG_READ(dac, FFBDAC_CFG_EPNP);
350 state->einp = DACCFG_READ(dac, FFBDAC_CFG_EINP);
351 state->eiap = DACCFG_READ(dac, FFBDAC_CFG_EIAP);
358 ffb_dacPtr dac = pFfb->dac;
374 did = DACCFG_READ(dac, FFBDAC_CFG_DID);
376 manuf_rev = DACCFG_READ(dac, FFBDAC_CFG_UCTRL);
420 /* Save the kernel DAC state. We also save to the
482 /* Restore X server DAC state. */
488 /* Save kernel DAC state. */
491 /* Restore X DAC state. */
495 /* Restore kernel DAC state. */
501 /* Save X DAC state. */
504 /* Restore kernel DAC and x-channel state. */
533 ffb_dacPtr dac;
537 else dac = pFfb -> dac;
545 tmp = DACCFG_READ(dac, FFBDAC_CFG_TGEN); /* Get the timing information */
564 DACCFG_WRITE(dac, FFBDAC_CFG_TGEN, tmp);
565 SPIN(dac, DPMS_SPIN_COUNT/10);
610 ffb_dacPtr dac = pFfb -> dac;
612 tmp = DACCFG_READ(dac, FFBDAC_CFG_TGEN); /* Get timing control */
643 DACCFG_WRITE(dac, FFBDAC_CFG_TGEN,tmp); /* Restore timing register, video set as asked */
644 SPIN(dac, DPMS_SPIN_COUNT); /* Is this necessary? Why? */
Indexes created Mon Jul 20 00:27:07 UTC 2026