Cross Reference: /xsrc/external/mit/xf86-video-tseng/dist/src/tseng

Lines Matching refs:Regs
255 STG1703PrintRegs(ScrnInfoPtr pScrn, struct STG1703Regs *Regs)
259                    Regs->Command);
261                    Regs->Pixel);
263                    Regs->Timing);
265                    Regs->PLL);
272 STG1703Store(ScrnInfoPtr pScrn, struct STG1703Regs *Regs)
283     Regs->Command = hwp->readDacMask(hwp);
291     hwp->writeDacMask(hwp, Regs->Command | 0x10);
303     Regs->Pixel = hwp->readDacMask(hwp); /* pixel mode */
307     Regs->Timing = hwp->readDacMask(hwp); /* pipeline timing */
321     Regs->PLL = hwp->readDacMask(hwp);
322     Regs->PLL |= (hwp->readDacMask(hwp) << 8);
330     hwp->writeDacMask(hwp, Regs->Command);
337     STG1703PrintRegs(pScrn, Regs);
344 STG1703Restore(ScrnInfoPtr pScrn, struct STG1703Regs *Regs)
349     STG1703PrintRegs(pScrn, Regs);
377     hwp->writeDacMask(hwp, Regs->Pixel); /* pixel mode */
378     hwp->writeDacMask(hwp, Regs->Pixel); /* also secondary */
379     hwp->writeDacMask(hwp, Regs->Timing); /* pipeline timing */
393     hwp->writeDacMask(hwp, Regs->PLL & 0xFF);
394     hwp->writeDacMask(hwp, Regs->PLL >> 8);
402     hwp->writeDacMask(hwp, Regs->Command);
461  * Copy the given Regs into a freshly alloced STG1703Regs
468     struct STG1703Regs *Regs;
470     Regs = xnfalloc(sizeof(struct STG1703Regs));
471     memcpy(Regs, Saved, sizeof(struct STG1703Regs));
473     Regs->Command &= 0x04; /* keep 7.5 IRE setup setting */
474     Regs->Command |= 0x08; /* enable extended pixel modes */
478         Regs->Pixel = 0x05;
482         Regs->Pixel = 0x03;
483         Regs->Command |= 0xC0; /* 16bpp */
486         Regs->Pixel = 0x09;
487         Regs->Command |= 0xE0; /* 24bpp */
490         Regs->Pixel = 0x04; /* 24bpp in 4Bytes */
491         Regs->Command |= 0xE0; /* 24bpp */
494         Regs->Pixel = 0x00;
501         Regs->Timing = 0;
503         Regs->Timing = 1;
505         Regs->Timing = 2;
507         Regs->Timing = 3;
510     Regs->PLL = STG1703Clock(pScrn, mode->Clock);
512     STG1703PrintRegs(pScrn, Regs);
514     return Regs;
563 CH8398PrintRegs(ScrnInfoPtr pScrn, struct CH8398Regs *Regs)
567                    Regs->Control);
569                    Regs->Aux);
571                    Regs->PLL);
578 CH8398Store(ScrnInfoPtr pScrn, struct CH8398Regs *Regs)
588     Regs->Control = hwp->readDacMask(hwp);
589     Regs->Aux = hwp->readDacMask(hwp);
598     hwp->writeDacMask(hwp, Regs->Aux | 0x80);
602     Regs->PLL = hwp->readDacData(hwp); /* N */
603     Regs->PLL |= hwp->readDacData(hwp) << 8; /* M and K*/
612     hwp->writeDacMask(hwp, Regs->Aux & ~0x80);
617     CH8398PrintRegs(pScrn, Regs);
624 CH8398Restore(ScrnInfoPtr pScrn, struct CH8398Regs *Regs)
628     CH8398PrintRegs(pScrn, Regs);
636     hwp->writeDacMask(hwp, Regs->Control);
637     hwp->writeDacMask(hwp, Regs->Aux | 0x80); /* enable PLL RAM mode as well */
641     hwp->writeDacData(hwp, Regs->PLL & 0xFF); /* N */
642     hwp->writeDacData(hwp, Regs->PLL >> 8); /* M and K */
651     hwp->writeDacMask(hwp, Regs->Aux & ~0x80);
711     struct CH8398Regs *Regs;
714     Regs = xnfalloc(sizeof(struct CH8398Regs));
715     memcpy(Regs, Saved, sizeof(struct CH8398Regs));
717     Regs->Control &= 0x0F;
721         Regs->Control |= 0x20;
724         Regs->Control |= 0x30;
727         Regs->Control |= 0xB0;
730         Regs->Control |= 0x50; /* 24bpp in 4bytes */
737     Regs->PLL = CH8398Clock(pScrn, Clock);
739     CH8398PrintRegs(pScrn, Regs);
741     return Regs;