Lines Matching refs:Clock
415 STG1703Clock(ScrnInfoPtr pScrn, int Clock)
427 temp = Clock * divider;
432 temp = (2 * Clock * divider) / 14318;
445 if (temp > Clock)
446 temp -= Clock;
448 temp = Clock - temp;
510 Regs->PLL = STG1703Clock(pScrn, mode->Clock);
661 Clock)
667 if (Clock > 68000)
677 temp = (2 * Clock * divider) / 14318;
690 if (temp > Clock)
691 temp -= Clock;
693 temp = Clock - temp;
712 int Clock = mode->Clock;
737 Regs->PLL = CH8398Clock(pScrn, Clock);
789 * This code evaluates a video mode with respect to requested dot clock
793 * For each mode, the minimum of max data transfer speed (dot clock
812 * "Besides the 135 MHz maximum pixel clock frequency, the other limit has to
817 * (system/memory) clock of 92 MHz (which is what we currently use) and
822 * current ET6000 chips. The ET6100 will raise the pixel clock limit
967 ErrorF("Clock parameters for %1.6f MHz: m=%d, n1=%d, n2=%d\n",
1267 mode->Clock = (mode->Clock * hmul) / 2;
1287 mode->name, mode->Clock, pScrn->bitsPerPixel);
1370 if ((mode->Clock * pTseng->Bytesperpixel) > 80000)
1393 /* prepare clock-related registers when not Legend.
1394 * cannot really SET the clock here yet, since the ET4000Save()
1412 /* setting min_n2 to "1" will ensure a more stable clock ("0" is allowed though) */
1417 if (mode->Clock * pTseng->Bytesperpixel > 130000) {
1448 * Set the clock selection bits. Because of the odd mapping between
1449 * Tseng clock select bits and what XFree86 does, "CSx" refers to a
1454 * Tseng register bit name XFree86 clock select bit
1467 /* clock select bit 4 = CS3 , clear CS4 */
Indexes created Wed Jul 01 00:25:26 UTC 2026