Cross Reference: /xsrc/external/mit/xorg-server.old/dist/hw/xfree86/ramdac/IBM.c

Lines Matching refs:DacRegs
195 	        (pScrn, i, (ramdacReg->DacRegs[i] & 0xFF00) >> 8, 
196 						ramdacReg->DacRegs[i]);
225 	    ramdacReg->DacRegs[i] = (*ramdacPtr->ReadDAC)(pScrn, i);
324     ramdacReg->DacRegs[IBMRGB_key_control] = 0x00; /* Disable Chroma Key */
328 	    ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_32BPP;
329 	    ramdacReg->DacRegs[IBMRGB_32bpp] = B32_DCOL_DIRECT;
330 	    ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
331 	    ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
332 	    ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
334 		ramdacReg->DacRegs[IBMRGB_key_control] = 0x01; /* Enable Key */
335 		ramdacReg->DacRegs[IBMRGB_key] = 0xFF; 
336 		ramdacReg->DacRegs[IBMRGB_key_mask] = 0xFF;
340 	    ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_24BPP;
341 	    ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
342 	    ramdacReg->DacRegs[IBMRGB_24bpp] = B24_DCOL_DIRECT;
343 	    ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
344 	    ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
348 	        ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_16BPP;
349 	        ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
350 	        ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
351 	        ramdacReg->DacRegs[IBMRGB_16bpp] = B16_DCOL_DIRECT|B16_LINEAR |
353 	        ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
355 	        ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_16BPP;
356 	        ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
357 	        ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
358 	        ramdacReg->DacRegs[IBMRGB_16bpp] = B16_DCOL_DIRECT|B16_LINEAR |
360 	        ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
364 	    ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_8BPP;
365 	    ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
366 	    ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
367 	    ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
368 	    ramdacReg->DacRegs[IBMRGB_8bpp] = B8_DCOL_INDIRECT;
371 	    ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_4BPP;
372 	    ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
373 	    ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
374 	    ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
375 	    ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
391     ramdacReg->DacRegs[RGB640_SER_WID_03_00] = 0x00;
392     ramdacReg->DacRegs[RGB640_SER_WID_07_04] = 0x00;
393     ramdacReg->DacRegs[RGB640_DIAGS] = 0x07;
397 	    ramdacReg->DacRegs[RGB640_SER_07_00] = 0x00; 
398 	    ramdacReg->DacRegs[RGB640_SER_15_08] = 0x00;
399 	    ramdacReg->DacRegs[RGB640_SER_23_16] = 0x00;
400 	    ramdacReg->DacRegs[RGB640_SER_31_24] = 0x00;
401     	    ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_16_1; /*16:1 Mux*/
402     	    ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PCLK_8; /* pll / 8 */
406 	    ramdacReg->DacRegs[RGB640_SER_07_00] = 0x10;
407 	    ramdacReg->DacRegs[RGB640_SER_15_08] = 0x11;
408 	    ramdacReg->DacRegs[RGB640_SER_23_16] = 0x00;
409 	    ramdacReg->DacRegs[RGB640_SER_31_24] = 0x00;
410     	    ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_8_1; /* 8:1 Mux*/
411     	    ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PCLK_8; /* pll / 8 */
415 	    ramdacReg->DacRegs[RGB640_SER_07_00] = 0x10;
416 	    ramdacReg->DacRegs[RGB640_SER_15_08] = 0x11;
417 	    ramdacReg->DacRegs[RGB640_SER_23_16] = 0x00;
418 	    ramdacReg->DacRegs[RGB640_SER_31_24] = 0x00;
419     	    ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_8_1; /* 8:1 Mux*/
420     	    ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PCLK_8; /* pll / 8 */
424 	    ramdacReg->DacRegs[RGB640_SER_07_00] = 0x30; 
425 	    ramdacReg->DacRegs[RGB640_SER_15_08] = 0x31;
426 	    ramdacReg->DacRegs[RGB640_SER_23_16] = 0x32;
427 	    ramdacReg->DacRegs[RGB640_SER_31_24] = 0x33;
428     	    ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_4_1; /* 4:1 Mux*/
429     	    ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PCLK_8; /* pll / 8 */
432 		ramdacReg->DacRegs[RGB640_SER_WID_07_04] = 0x04;
433 		ramdacReg->DacRegs[RGB640_CHROMA_KEY0] = 0xFF;
434 		ramdacReg->DacRegs[RGB640_CHROMA_MASK0] = 0xFF;
441 	    ramdacReg->DacRegs[RGB640_SER_07_00] = 0x30; 
442 	    ramdacReg->DacRegs[RGB640_SER_15_08] = 0x31;
443 	    ramdacReg->DacRegs[RGB640_SER_23_16] = 0x32;
444 	    ramdacReg->DacRegs[RGB640_SER_31_24] = 0x33;
445     	    ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_4_1; /* 4:1 Mux*/
446     	    ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PSIZE10 | 
456 	    ramdacReg->DacRegs[i+0] = bpp;
457 	    ramdacReg->DacRegs[i+1] = offset;
458 	    ramdacReg->DacRegs[i+2] = 0x00;
459 	    ramdacReg->DacRegs[i+3] = 0x00;
461 	    ramdacReg->DacRegs[i+0x100] = overlaybpp;
462 	    ramdacReg->DacRegs[i+0x101] = 0x00;
463 	    ramdacReg->DacRegs[i+0x102] = 0x00;
464 	    ramdacReg->DacRegs[i+0x103] = dispcont;