Cross Reference: /xsrc/external/mit/xorg-server.old/dist/hw/xfree86/ramdac/TI.c

Lines Matching refs:DacRegs
160     if (ramdacReg->DacRegs[TIDAC_PIXEL_VALID]) {
168 					ramdacReg->DacRegs[TIDAC_PIXEL_N]);
170 					ramdacReg->DacRegs[TIDAC_PIXEL_M]);
172 					ramdacReg->DacRegs[TIDAC_PIXEL_P]);
186     if (ramdacReg->DacRegs[TIDAC_LOOP_VALID]) {
194 					ramdacReg->DacRegs[TIDAC_LOOP_N]);
196 					ramdacReg->DacRegs[TIDAC_LOOP_M]);
198 					ramdacReg->DacRegs[TIDAC_LOOP_P]);
238     ramdacReg->DacRegs[TIDAC_PIXEL_N] = 
241     ramdacReg->DacRegs[TIDAC_PIXEL_M] = 
244     ramdacReg->DacRegs[TIDAC_PIXEL_P] = 
249     ramdacReg->DacRegs[TIDAC_LOOP_N] = 
252     ramdacReg->DacRegs[TIDAC_LOOP_M] = 
255     ramdacReg->DacRegs[TIDAC_LOOP_P] = 
360 	ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
361 	ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
362 	ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5c;
363 	ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
364 	ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
365 	ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
366 	ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
368 	ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
369 	ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
370 	ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
371 	ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
372 	ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
373 	ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
374 	ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
375 	ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
376 	ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
377 	ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
379 	    ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
380 	    ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
381 	    ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
383 	ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
387 	ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
388 	ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
389 	ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
390 	ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
391 	ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
392 	ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
393 	ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
395 	ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
396 	ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
397 	ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
398 	ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
399 	ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
400 	ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
401 	ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
402 	ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
403 	ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
404 	ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
405 	ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
411 	ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
413 	ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
416 	    ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
418 	    ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
422 	ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
423 	ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
424 	ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
425 	ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
427 	ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x54;
428 	ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
429 	ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
430 	ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
432 	ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
434 	ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
435 	ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
436 	ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
437 	ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
438 	ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
439 	ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
440 	ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
441 	ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
442 	ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
443 	ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
444 	ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
448 	ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
449 	ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
450 	ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4c;
451 	ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
452 	ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
453 	ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
454 	ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
456 	ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
457 	ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
458 	ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
459 	ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
460 	ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
461 	ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
462 	ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
463 	ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
464 	ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
465 	ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
466 	ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
477 	ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
478 	ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
479 	ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5D;
480 	ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
481 	ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
482 	ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
483 	ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
485 	ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
486 	ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
487 	ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
488 	ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
489 	ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
490 	ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
491 	ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
492 	ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
493 	ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
494 	ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
496 	    ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
497 	    ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
498 	    ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
500 	ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
504 	ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
505 	ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
506 	ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
507 	ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
508 	ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
509 	ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
510 	ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
512 	ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
513 	ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
514 	ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
515 	ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
516 	ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
517 	ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
518 	ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
519 	ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
520 	ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
521 	ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
522 	ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
528 	ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
530 	ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
533 	    ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
535 	    ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
539 	ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
540 	ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
541 	ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
542 	ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
544 	ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x55;
545 	ramdacReg->DacRegs[TIDAC_clock_select] = 0x85;
546 	ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
547 	ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
549 	ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
551 	ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
552 	ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
553 	ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
554 	ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
555 	ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
556 	ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
557 	ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
558 	ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
559 	ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
560 	ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
561 	ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
565 	ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
566 	ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
567 	ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4d;
568 	ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
569 	ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
570 	ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
571 	ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
573 	ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
574 	ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
575 	ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
576 	ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
577 	ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
578 	ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
579 	ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
580 	ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
581 	ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
582 	ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
583 	ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;