1 /* $NetBSD: sun4i_a10_ccu.h,v 1.1 2017/10/06 21:09:21 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _SUN4I_A10_CCU_H 30 #define _SUN4I_A10_CCU_H 31 32 #define A10_RST_USB_PHY0 1 33 #define A10_RST_USB_PHY1 2 34 #define A10_RST_USB_PHY2 3 35 #define A10_RST_GPS 4 36 #define A10_RST_DE_BE0 5 37 #define A10_RST_DE_BE1 6 38 #define A10_RST_DE_FE0 7 39 #define A10_RST_DE_FE1 8 40 #define A10_RST_DE_MP 9 41 #define A10_RST_TVE0 10 42 #define A10_RST_TCON0 11 43 #define A10_RST_TVE1 12 44 #define A10_RST_TCON1 13 45 #define A10_RST_CSI0 14 46 #define A10_RST_CSI1 15 47 #define A10_RST_VE 16 48 #define A10_RST_ACE 17 49 #define A10_RST_LVDS 18 50 #define A10_RST_GPU 19 51 #define A10_RST_HDMI_H 20 52 #define A10_RST_HDMI_SYS 21 53 #define A10_RST_HDMI_AUDIO_DM 22 54 55 #define A10_CLK_HOSC 1 56 #define A10_CLK_PLL_CORE 2 57 #define A10_CLK_PLL_AUDIO_BASE 3 58 #define A10_CLK_PLL_AUDIO 4 59 #define A10_CLK_PLL_AUDIO_2X 5 60 #define A10_CLK_PLL_AUDIO_4X 6 61 #define A10_CLK_PLL_AUDIO_8X 7 62 #define A10_CLK_PLL_VIDEO0 8 63 #define A10_CLK_PLL_VIDEO0_2X 9 64 #define A10_CLK_PLL_VE 10 65 #define A10_CLK_PLL_DDR_BASE 11 66 #define A10_CLK_PLL_DDR 12 67 #define A10_CLK_PLL_DDR_OTHER 13 68 #define A10_CLK_PLL_PERIPH_BASE 14 69 #define A10_CLK_PLL_PERIPH 15 70 #define A10_CLK_PLL_PERIPH_SATA 16 71 #define A10_CLK_PLL_VIDEO1 17 72 #define A10_CLK_PLL_VIDEO1_2X 18 73 #define A10_CLK_PLL_GPU 19 74 #define A10_CLK_CPU 20 75 #define A10_CLK_AXI 21 76 #define A10_CLK_AXI_DRAM 22 77 #define A10_CLK_AHB 23 78 #define A10_CLK_APB0 24 79 #define A10_CLK_APB1 25 80 #define A10_CLK_AHB_OTG 26 81 #define A10_CLK_AHB_EHCI0 27 82 #define A10_CLK_AHB_OHCI0 28 83 #define A10_CLK_AHB_EHCI1 29 84 #define A10_CLK_AHB_OHCI1 30 85 #define A10_CLK_AHB_SS 31 86 #define A10_CLK_AHB_DMA 32 87 #define A10_CLK_AHB_BIST 33 88 #define A10_CLK_AHB_MMC0 34 89 #define A10_CLK_AHB_MMC1 35 90 #define A10_CLK_AHB_MMC2 36 91 #define A10_CLK_AHB_MMC3 37 92 #define A10_CLK_AHB_MS 38 93 #define A10_CLK_AHB_NAND 39 94 #define A10_CLK_AHB_SDRAM 40 95 #define A10_CLK_AHB_ACE 41 96 #define A10_CLK_AHB_EMAC 42 97 #define A10_CLK_AHB_TS 43 98 #define A10_CLK_AHB_SPI0 44 99 #define A10_CLK_AHB_SPI1 45 100 #define A10_CLK_AHB_SPI2 46 101 #define A10_CLK_AHB_SPI3 47 102 #define A10_CLK_AHB_PATA 48 103 #define A10_CLK_AHB_SATA 49 104 #define A10_CLK_AHB_GPS 50 105 #define A10_CLK_AHB_HSTIMER 51 106 #define A10_CLK_AHB_VE 52 107 #define A10_CLK_AHB_TVD 53 108 #define A10_CLK_AHB_TVE0 54 109 #define A10_CLK_AHB_TVE1 55 110 #define A10_CLK_AHB_LCD0 56 111 #define A10_CLK_AHB_LCD1 57 112 #define A10_CLK_AHB_CSI0 58 113 #define A10_CLK_AHB_CSI1 59 114 #define A10_CLK_AHB_HDMI0 60 115 #define A10_CLK_AHB_HDMI1 61 116 #define A10_CLK_AHB_DE_BE0 62 117 #define A10_CLK_AHB_DE_BE1 63 118 #define A10_CLK_AHB_DE_FE0 64 119 #define A10_CLK_AHB_DE_FE1 65 120 #define A10_CLK_AHB_GMAC 66 121 #define A10_CLK_AHB_MP 67 122 #define A10_CLK_AHB_GPU 68 123 #define A10_CLK_APB0_CODEC 69 124 #define A10_CLK_APB0_SPDIF 70 125 #define A10_CLK_APB0_I2S0 71 126 #define A10_CLK_APB0_AC97 72 127 #define A10_CLK_APB0_I2S1 73 128 #define A10_CLK_APB0_PIO 74 129 #define A10_CLK_APB0_IR0 75 130 #define A10_CLK_APB0_IR1 76 131 #define A10_CLK_APB0_I2S2 77 132 #define A10_CLK_APB0_KEYPAD 78 133 #define A10_CLK_APB1_I2C0 79 134 #define A10_CLK_APB1_I2C1 80 135 #define A10_CLK_APB1_I2C2 81 136 #define A10_CLK_APB1_I2C3 82 137 #define A10_CLK_APB1_CAN 83 138 #define A10_CLK_APB1_SCR 84 139 #define A10_CLK_APB1_PS20 85 140 #define A10_CLK_APB1_PS21 86 141 #define A10_CLK_APB1_I2C4 87 142 #define A10_CLK_APB1_UART0 88 143 #define A10_CLK_APB1_UART1 89 144 #define A10_CLK_APB1_UART2 90 145 #define A10_CLK_APB1_UART3 91 146 #define A10_CLK_APB1_UART4 92 147 #define A10_CLK_APB1_UART5 93 148 #define A10_CLK_APB1_UART6 94 149 #define A10_CLK_APB1_UART7 95 150 #define A10_CLK_NAND 96 151 #define A10_CLK_MS 97 152 #define A10_CLK_MMC0 98 153 #define A10_CLK_MMC0_OUTPUT 99 154 #define A10_CLK_MMC0_SAMPLE 100 155 #define A10_CLK_MMC1 101 156 #define A10_CLK_MMC1_OUTPUT 102 157 #define A10_CLK_MMC1_SAMPLE 103 158 #define A10_CLK_MMC2 104 159 #define A10_CLK_MMC2_OUTPUT 105 160 #define A10_CLK_MMC2_SAMPLE 106 161 #define A10_CLK_MMC3 107 162 #define A10_CLK_MMC3_OUTPUT 108 163 #define A10_CLK_MMC3_SAMPLE 109 164 #define A10_CLK_TS 110 165 #define A10_CLK_SS 111 166 #define A10_CLK_SPI0 112 167 #define A10_CLK_SPI1 113 168 #define A10_CLK_SPI2 114 169 #define A10_CLK_PATA 115 170 #define A10_CLK_IR0 116 171 #define A10_CLK_IR1 117 172 #define A10_CLK_I2S0 118 173 #define A10_CLK_AC97 119 174 #define A10_CLK_SPDIF 120 175 #define A10_CLK_KEYPAD 121 176 #define A10_CLK_SATA 122 177 #define A10_CLK_USB_OHCI0 123 178 #define A10_CLK_USB_OHCI1 124 179 #define A10_CLK_USB_PHY 125 180 #define A10_CLK_GPS 126 181 #define A10_CLK_SPI3 127 182 #define A10_CLK_I2S1 128 183 #define A10_CLK_I2S2 129 184 #define A10_CLK_DRAM_VE 130 185 #define A10_CLK_DRAM_CSI0 131 186 #define A10_CLK_DRAM_CSI1 132 187 #define A10_CLK_DRAM_TS 133 188 #define A10_CLK_DRAM_TVD 134 189 #define A10_CLK_DRAM_TVE0 135 190 #define A10_CLK_DRAM_TVE1 136 191 #define A10_CLK_DRAM_OUT 137 192 #define A10_CLK_DRAM_DE_FE1 138 193 #define A10_CLK_DRAM_DE_FE0 139 194 #define A10_CLK_DRAM_DE_BE0 140 195 #define A10_CLK_DRAM_DE_BE1 141 196 #define A10_CLK_DRAM_MP 142 197 #define A10_CLK_DRAM_ACE 143 198 #define A10_CLK_DE_BE0 144 199 #define A10_CLK_DE_BE1 145 200 #define A10_CLK_DE_FE0 146 201 #define A10_CLK_DE_FE1 147 202 #define A10_CLK_DE_MP 148 203 #define A10_CLK_TCON0_CH0 149 204 #define A10_CLK_TCON1_CH0 150 205 #define A10_CLK_CSI_SCLK 151 206 #define A10_CLK_TVD_SCLK2 152 207 #define A10_CLK_TVD 153 208 #define A10_CLK_TCON0_CH1_SCLK2 154 209 #define A10_CLK_TCON0_CH1 155 210 #define A10_CLK_TCON1_CH1_SCLK2 156 211 #define A10_CLK_TCON1_CH1 157 212 #define A10_CLK_CSI0 158 213 #define A10_CLK_CSI1 159 214 #define A10_CLK_CODEC 160 215 #define A10_CLK_VE 161 216 #define A10_CLK_AVS 162 217 #define A10_CLK_ACE 163 218 #define A10_CLK_HDMI 164 219 #define A10_CLK_GPU 165 220 221 #endif /* !_SUN4I_A10_CCU_H */ 222
Indexes created Wed Oct 01 19:09:53 GMT 2025