1 /* $NetBSD: sun6i_a31_ccu.h,v 1.1 2017/07/02 00:14:09 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __CCU_A31_H__ 32 #define __CCU_A31_H__ 33 34 #define A31_RST_USB_PHY0 0 35 #define A31_RST_USB_PHY1 1 36 #define A31_RST_USB_PHY2 2 37 #define A31_RST_AHB1_MIPI_DSI 3 38 #define A31_RST_AHB1_SS 4 39 #define A31_RST_AHB1_DMA 5 40 #define A31_RST_AHB1_MMC0 6 41 #define A31_RST_AHB1_MMC1 7 42 #define A31_RST_AHB1_MMC2 8 43 #define A31_RST_AHB1_MMC3 9 44 #define A31_RST_AHB1_NAND1 10 45 #define A31_RST_AHB1_NAND0 11 46 #define A31_RST_AHB1_SDRAM 12 47 #define A31_RST_AHB1_EMAC 13 48 #define A31_RST_AHB1_TS 14 49 #define A31_RST_AHB1_HSTIMER 15 50 #define A31_RST_AHB1_SPI0 16 51 #define A31_RST_AHB1_SPI1 17 52 #define A31_RST_AHB1_SPI2 18 53 #define A31_RST_AHB1_SPI3 19 54 #define A31_RST_AHB1_OTG 20 55 #define A31_RST_AHB1_EHCI0 21 56 #define A31_RST_AHB1_EHCI1 22 57 #define A31_RST_AHB1_OHCI0 23 58 #define A31_RST_AHB1_OHCI1 24 59 #define A31_RST_AHB1_OHCI2 25 60 #define A31_RST_AHB1_VE 26 61 #define A31_RST_AHB1_LCD0 27 62 #define A31_RST_AHB1_LCD1 28 63 #define A31_RST_AHB1_CSI 29 64 #define A31_RST_AHB1_HDMI 30 65 #define A31_RST_AHB1_BE0 31 66 #define A31_RST_AHB1_BE1 32 67 #define A31_RST_AHB1_FE0 33 68 #define A31_RST_AHB1_FE1 34 69 #define A31_RST_AHB1_MP 35 70 #define A31_RST_AHB1_GPU 36 71 #define A31_RST_AHB1_DEU0 37 72 #define A31_RST_AHB1_DEU1 38 73 #define A31_RST_AHB1_DRC0 39 74 #define A31_RST_AHB1_DRC1 40 75 #define A31_RST_AHB1_LVDS 41 76 #define A31_RST_APB1_CODEC 42 77 #define A31_RST_APB1_SPDIF 43 78 #define A31_RST_APB1_DIGITAL_MIC 44 79 #define A31_RST_APB1_DAUDIO0 45 80 #define A31_RST_APB1_DAUDIO1 46 81 #define A31_RST_APB2_I2C0 47 82 #define A31_RST_APB2_I2C1 48 83 #define A31_RST_APB2_I2C2 49 84 #define A31_RST_APB2_I2C3 50 85 #define A31_RST_APB2_UART0 51 86 #define A31_RST_APB2_UART1 52 87 #define A31_RST_APB2_UART2 53 88 #define A31_RST_APB2_UART3 54 89 #define A31_RST_APB2_UART4 55 90 #define A31_RST_APB2_UART5 56 91 92 #define A31_CLK_PLL_CPU 0 93 #define A31_CLK_PLL_AUDIO_BASE 1 94 #define A31_CLK_PLL_AUDIO 2 95 #define A31_CLK_PLL_AUDIO_2X 3 96 #define A31_CLK_PLL_AUDIO_4X 4 97 #define A31_CLK_PLL_AUDIO_8X 5 98 #define A31_CLK_PLL_VIDEO0 6 99 #define A31_CLK_PLL_VIDEO0_2X 7 100 #define A31_CLK_PLL_VE 8 101 #define A31_CLK_PLL_DDR 9 102 #define A31_CLK_PLL_PERIPH 10 103 #define A31_CLK_PLL_PERIPH_2X 11 104 #define A31_CLK_PLL_VIDEO1 12 105 #define A31_CLK_PLL_VIDEO1_2X 13 106 #define A31_CLK_PLL_GPU 14 107 #define A31_CLK_PLL_MIPI 15 108 #define A31_CLK_PLL9 16 109 #define A31_CLK_PLL10 17 110 #define A31_CLK_CPU 18 111 #define A31_CLK_AXI 19 112 #define A31_CLK_AHB1 20 113 #define A31_CLK_APB1 21 114 #define A31_CLK_APB2 22 115 #define A31_CLK_AHB1_MIPIDSI 23 116 #define A31_CLK_AHB1_SS 24 117 #define A31_CLK_AHB1_DMA 25 118 #define A31_CLK_AHB1_MMC0 26 119 #define A31_CLK_AHB1_MMC1 27 120 #define A31_CLK_AHB1_MMC2 28 121 #define A31_CLK_AHB1_MMC3 29 122 #define A31_CLK_AHB1_NAND1 30 123 #define A31_CLK_AHB1_NAND0 31 124 #define A31_CLK_AHB1_SDRAM 32 125 #define A31_CLK_AHB1_EMAC 33 126 #define A31_CLK_AHB1_TS 34 127 #define A31_CLK_AHB1_HSTIMER 35 128 #define A31_CLK_AHB1_SPI0 36 129 #define A31_CLK_AHB1_SPI1 37 130 #define A31_CLK_AHB1_SPI2 38 131 #define A31_CLK_AHB1_SPI3 39 132 #define A31_CLK_AHB1_OTG 40 133 #define A31_CLK_AHB1_EHCI0 41 134 #define A31_CLK_AHB1_EHCI1 42 135 #define A31_CLK_AHB1_OHCI0 43 136 #define A31_CLK_AHB1_OHCI1 44 137 #define A31_CLK_AHB1_OHCI2 45 138 #define A31_CLK_AHB1_VE 46 139 #define A31_CLK_AHB1_LCD0 47 140 #define A31_CLK_AHB1_LCD1 48 141 #define A31_CLK_AHB1_CSI 49 142 #define A31_CLK_AHB1_HDMI 50 143 #define A31_CLK_AHB1_BE0 51 144 #define A31_CLK_AHB1_BE1 52 145 #define A31_CLK_AHB1_FE0 53 146 #define A31_CLK_AHB1_FE1 54 147 #define A31_CLK_AHB1_MP 55 148 #define A31_CLK_AHB1_GPU 56 149 #define A31_CLK_AHB1_DEU0 57 150 #define A31_CLK_AHB1_DEU1 58 151 #define A31_CLK_AHB1_DRC0 59 152 #define A31_CLK_AHB1_DRC1 60 153 #define A31_CLK_APB1_CODEC 61 154 #define A31_CLK_APB1_SPDIF 62 155 #define A31_CLK_APB1_DIGITAL_MIC 63 156 #define A31_CLK_APB1_PIO 64 157 #define A31_CLK_APB1_DAUDIO0 65 158 #define A31_CLK_APB1_DAUDIO1 66 159 #define A31_CLK_APB2_I2C0 67 160 #define A31_CLK_APB2_I2C1 68 161 #define A31_CLK_APB2_I2C2 69 162 #define A31_CLK_APB2_I2C3 70 163 #define A31_CLK_APB2_UART0 71 164 #define A31_CLK_APB2_UART1 72 165 #define A31_CLK_APB2_UART2 73 166 #define A31_CLK_APB2_UART3 74 167 #define A31_CLK_APB2_UART4 75 168 #define A31_CLK_APB2_UART5 76 169 #define A31_CLK_NAND0 77 170 #define A31_CLK_NAND1 78 171 #define A31_CLK_MMC0 79 172 #define A31_CLK_MMC0_SAMPLE 80 173 #define A31_CLK_MMC0_OUTPUT 81 174 #define A31_CLK_MMC1 82 175 #define A31_CLK_MMC1_SAMPLE 83 176 #define A31_CLK_MMC1_OUTPUT 84 177 #define A31_CLK_MMC2 85 178 #define A31_CLK_MMC2_SAMPLE 86 179 #define A31_CLK_MMC2_OUTPUT 87 180 #define A31_CLK_MMC3 88 181 #define A31_CLK_MMC3_SAMPLE 89 182 #define A31_CLK_MMC3_OUTPUT 90 183 #define A31_CLK_TS 91 184 #define A31_CLK_SS 92 185 #define A31_CLK_SPI0 93 186 #define A31_CLK_SPI1 94 187 #define A31_CLK_SPI2 95 188 #define A31_CLK_SPI3 96 189 #define A31_CLK_DAUDIO0 97 190 #define A31_CLK_DAUDIO1 98 191 #define A31_CLK_SPDIF 99 192 #define A31_CLK_USB_PHY0 100 193 #define A31_CLK_USB_PHY1 101 194 #define A31_CLK_USB_PHY2 102 195 #define A31_CLK_USB_OHCI0 103 196 #define A31_CLK_USB_OHCI1 104 197 #define A31_CLK_USB_OHCI2 105 198 #define A31_CLK_MDFS 107 199 #define A31_CLK_SDRAM0 108 200 #define A31_CLK_SDRAM1 109 201 #define A31_CLK_DRAM_VE 110 202 #define A31_CLK_DRAM_CSI_ISP 111 203 #define A31_CLK_DRAM_TS 112 204 #define A31_CLK_DRAM_DRC0 113 205 #define A31_CLK_DRAM_DRC1 114 206 #define A31_CLK_DRAM_DEU0 115 207 #define A31_CLK_DRAM_DEU1 116 208 #define A31_CLK_DRAM_FE0 117 209 #define A31_CLK_DRAM_FE1 118 210 #define A31_CLK_DRAM_BE0 119 211 #define A31_CLK_DRAM_BE1 120 212 #define A31_CLK_DRAM_MP 121 213 #define A31_CLK_BE0 122 214 #define A31_CLK_BE1 123 215 #define A31_CLK_FE0 124 216 #define A31_CLK_FE1 125 217 #define A31_CLK_MP 126 218 #define A31_CLK_LCD0_CH0 127 219 #define A31_CLK_LCD1_CH0 128 220 #define A31_CLK_LCD0_CH1 129 221 #define A31_CLK_LCD1_CH1 130 222 #define A31_CLK_CSI0_SCLK 131 223 #define A31_CLK_CSI0_MCLK 132 224 #define A31_CLK_CSI1_MCLK 133 225 #define A31_CLK_VE 134 226 #define A31_CLK_CODEC 135 227 #define A31_CLK_AVS 136 228 #define A31_CLK_DIGITAL_MIC 137 229 #define A31_CLK_HDMI 138 230 #define A31_CLK_HDMI_DDC 139 231 #define A31_CLK_PS 140 232 #define A31_CLK_MBUS0 141 233 #define A31_CLK_MBUS1 142 234 #define A31_CLK_MIPI_DSI 143 235 #define A31_CLK_MIPI_DSI_DPHY 144 236 #define A31_CLK_MIPI_CSI_DPHY 145 237 #define A31_CLK_IEP_DRC0 146 238 #define A31_CLK_IEP_DRC1 147 239 #define A31_CLK_IEP_DEU0 148 240 #define A31_CLK_IEP_DEU1 149 241 #define A31_CLK_GPU_CORE 150 242 #define A31_CLK_GPU_MEMORY 151 243 #define A31_CLK_GPU_HYD 152 244 #define A31_CLK_ATS 153 245 #define A31_CLK_TRACE 154 246 #define A31_CLK_OUT_A 155 247 #define A31_CLK_OUT_B 156 248 #define A31_CLK_OUT_C 157 249 250 #endif /* __CCU_A31 H__ */ 251
Indexes created Thu Oct 02 14:10:14 GMT 2025