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  /src/external/apache2/llvm/dist/llvm/lib/Support/
ARMWinEH.cpp 1 //===-- ARMWinEH.cpp - Windows on ARM EH Support Functions ------*- C++ -*-===//
13 namespace ARM {
35 } // namespace ARM
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMMCTargetDesc.h 1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
9 // This file provides ARM specific target descriptions.
60 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
102 /// Construct an ARM Mach-O object writer.
107 /// Construct an ARM PE/COFF object writer.
111 /// Construct ARM Mach-O relocation info.
114 namespace ARM {
128 } // end namespace ARM
132 // Defines symbolic names for ARM registers. This defines a mapping from
138 // Defines symbolic names for the ARM instructions
    [all...]
ARMFixupKinds.h 1 //===-- ARMFixupKinds.h - ARM Specific Fixup Entries ------------*- C++ -*-===//
15 namespace ARM {
62 // The following fixups handle the ARM BL instructions. These can be
63 // conditionalised; however, the ARM ELF ABI requires a different relocation
71 // Fixup for unconditional ARM BL instructions.
74 // Fixup for ARM BL instructions with nontrivial conditionalisation.
77 // Fixup for ARM BLX instructions.
  /src/external/apache2/llvm/dist/llvm/tools/llvm-readobj/
ARMWinEHPrinter.h 1 //===--- ARMWinEHPrinter.h - Windows on ARM Unwind Information Printer ----===//
17 namespace ARM {
ARMEHABIPrinter.h 1 //===--- ARMEHABIPrinter.h - ARM EHABI Unwind Information Printer ----------===//
24 namespace ARM {
125 SW.startLine() << format("0x%02X ; reserved (ARM MOVrr)\n", Opcode);
454 /// ARM EHABI Section 6.2 - The generic model
466 /// ARM EHABI Section 6.3 - The ARM-defined compact model
526 /// ARM EHABI Section 5 - Index Table Entries
573 // In a relocatable output we might have many .ARM.exidx sections linked to
575 // the sh_link field is not reliable, because we have one .ARM.exidx section
ARMWinEHPrinter.cpp 1 //===-- ARMWinEHPrinter.cpp - Windows on ARM EH Data Printer ----*- C++ -*-===//
9 // Windows on ARM uses a series of serialised data structures (RuntimeFunction)
48 // (c.f. ARM::WinEH::HeaderWords) and encodes most of the same information as
75 raw_ostream &operator<<(raw_ostream &OS, const ARM::WinEH::ReturnType &RT) {
77 case ARM::WinEH::ReturnType::RT_POP:
80 case ARM::WinEH::ReturnType::RT_B:
83 case ARM::WinEH::ReturnType::RT_BW:
86 case ARM::WinEH::ReturnType::RT_NoEpilogue:
113 namespace ARM {
918 // the unwind codes. Applicable to both ARM and AArch64
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMAsmPrinter.h 1 //===-- ARMAsmPrinter.h - ARM implementation of AsmPrinter ------*- C++ -*-===//
24 namespace ARM {
73 return "ARM Assembly Printer";
112 // XRay-specific lowering for ARM.
134 // ARM/Darwin adds ISA to the DWARF info for each function.
141 return isThumb ? ARM::DW_ISA_ARM_thumb : ARM::DW_ISA_ARM_arm;
ARMISelLowering.h 1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
9 // This file defines the interfaces that ARM uses to lower LLVM code into a
54 // ARM Specific DAG Nodes
85 CMP, // ARM compare instructions.
86 CMN, // ARM CMN instructions.
87 CMPZ, // ARM compare that sets only Z flag.
88 CMPFP, // ARM VFP compare instruction, sets FPSCR.
89 CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR.
90 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
91 CMPFPEw0, // ARM VFP signalling compare against zero instruction, set
    [all...]
ARMRegisterBankInfo.cpp 9 /// This file implements the targeting of the RegisterBankInfo class for ARM.
30 namespace ARM {
129 } // end namespace arm
137 // (ARM::RegBanks) is unique in the compiler. At some point, it
142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCTargetOptions.h 22 ARM, ///< ARM EHABI
MCAsmInfo.h 39 ARM, /// Windows NT (Windows on ARM)
40 CE, /// Windows CE ARM, PowerPC, SH3, SH4
763 ExceptionsType == ExceptionHandling::ARM || usesWindowsCFI());
  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
ARMEHABI.h 1 //===--- ARMEHABI.h - ARM Exception Handling ABI ----------------*- C++ -*-===//
9 // This file defines the constants for the ARM unwind opcodes and exception
12 // The enumerations and constants in this file reflect the ARM EHABI
13 // Specification as published by ARM.
15 // Exception Handling ABI for the ARM Architecture r2.09 - November 30, 2012
17 // http://infocenter.arm.com/help/topic/com.arm.doc.ihi0038a/IHI0038A_ehabi.pdf
25 namespace ARM {
27 /// ARM exception handling table entry kinds
38 /// ARM-defined frame unwinding opcode
    [all...]
ARMTargetParser.h 1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
9 // This file implements a target parser to recognise ARM hardware features
26 namespace ARM {
126 {NAME, sizeof(NAME) - 1, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
163 enum class ISAKind { INVALID = 0, ARM, THUMB, AARCH64 };
175 // The entries must appear in the order listed in ARM::FPUKind for correct
196 // and Arch ID, according to the Addenda to the ARM ABI, chapters
252 bool appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK, StringRef ArchExt,
279 } // namespace ARM
ARMWinEH.h 1 //===-- llvm/Support/ARMWinEH.h - Windows on ARM EH Constants ---*- C++ -*-===//
16 namespace ARM {
34 /// This is ARM specific, but the Function Start RVA, Flag and
291 /// The format on ARM is:
321 /// skipped) (ARM only)
341 /// The epilogue scope format on ARM is:
363 /// Condition : (ARM only) 4-bit field providing the condition under which the
399 // Same for both ARM and AArch64.
404 // Different implementations for ARM and AArch64.
413 // Condition is only applicable to ARM
    [all...]
  /src/external/apache2/llvm/dist/llvm/tools/llvm-cxxfilt/
llvm-cxxfilt.cpp 25 ARM,
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Utils/
ARMBaseInfo.h 1 //===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===//
10 // the ARM target useful for the compiler back-end and the MC libraries.
26 // Enums corresponding to ARM condition codes
96 namespace ARM {
122 } // namespace ARM
127 ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask,
  /src/external/apache2/llvm/dist/clang/include/clang/Basic/
TargetBuiltins.h 35 /// ARM builtins
36 namespace ARM {
324 {ARM::LastTSBuiltin, AArch64::LastTSBuiltin, BPF::LastTSBuiltin,
  /src/games/battlestar/
extern.h 193 #define ARM 6 /* broken arm */
  /src/external/gpl3/binutils/dist/bfd/
coff-arm.c 1 /* BFD back-end for ARM COFF files.
25 #include "coff/arm.h"
27 #include "cpu-arm.h"
28 #include "coff-arm.h"
646 /* Now the ARM magic... Change the reloc type so that it is marked as done.
770 /* Now the ARM magic... Change the reloc type so that it is marked as done.
887 #define ARM 1 /* Customize coffcode.h. */
896 /* Extend the coff_link_hash_table structure with a few ARM specific fields.
904 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
907 /* The size in bytes of the section containing the ARM-to-Thumb glue. *
    [all...]
  /src/external/gpl3/binutils.old/dist/bfd/
coff-arm.c 1 /* BFD back-end for ARM COFF files.
25 #include "coff/arm.h"
27 #include "cpu-arm.h"
28 #include "coff-arm.h"
646 /* Now the ARM magic... Change the reloc type so that it is marked as done.
770 /* Now the ARM magic... Change the reloc type so that it is marked as done.
887 #define ARM 1 /* Customize coffcode.h. */
896 /* Extend the coff_link_hash_table structure with a few ARM specific fields.
904 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
907 /* The size in bytes of the section containing the ARM-to-Thumb glue. *
    [all...]
  /src/external/gpl3/gdb.old/dist/bfd/
coff-arm.c 1 /* BFD back-end for ARM COFF files.
25 #include "coff/arm.h"
27 #include "cpu-arm.h"
28 #include "coff-arm.h"
646 /* Now the ARM magic... Change the reloc type so that it is marked as done.
770 /* Now the ARM magic... Change the reloc type so that it is marked as done.
887 #define ARM 1 /* Customize coffcode.h. */
896 /* Extend the coff_link_hash_table structure with a few ARM specific fields.
904 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
907 /* The size in bytes of the section containing the ARM-to-Thumb glue. *
    [all...]
  /src/external/gpl3/gdb/dist/bfd/
coff-arm.c 1 /* BFD back-end for ARM COFF files.
25 #include "coff/arm.h"
27 #include "cpu-arm.h"
28 #include "coff-arm.h"
646 /* Now the ARM magic... Change the reloc type so that it is marked as done.
770 /* Now the ARM magic... Change the reloc type so that it is marked as done.
887 #define ARM 1 /* Customize coffcode.h. */
896 /* Extend the coff_link_hash_table structure with a few ARM specific fields.
904 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
907 /* The size in bytes of the section containing the ARM-to-Thumb glue. *
    [all...]
  /src/external/gpl3/binutils/dist/opcodes/
arm-dis.c 1 /* Instruction printing code for the ARM
27 #include "opcode/arm.h"
39 #include "elf/arm.h"
378 ARM
382 /* Shared (between Arm and Thumb mode) opcode. */
403 %c print condition code (always bits 28-31 in ARM mode)
406 %u print condition code (unconditional in ARM mode,
415 %<bitfield>r print as an ARM register
459 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
468 %<bitfield>r print as an ARM registe
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
arm-dis.c 1 /* Instruction printing code for the ARM
27 #include "opcode/arm.h"
39 #include "elf/arm.h"
378 ARM
382 /* Shared (between Arm and Thumb mode) opcode. */
403 %c print condition code (always bits 28-31 in ARM mode)
406 %u print condition code (unconditional in ARM mode,
415 %<bitfield>r print as an ARM register
459 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
468 %<bitfield>r print as an ARM registe
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
arm-dis.c 1 /* Instruction printing code for the ARM
27 #include "opcode/arm.h"
39 #include "elf/arm.h"
378 ARM
382 /* Shared (between Arm and Thumb mode) opcode. */
403 %c print condition code (always bits 28-31 in ARM mode)
406 %u print condition code (unconditional in ARM mode,
415 %<bitfield>r print as an ARM register
459 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
468 %<bitfield>r print as an ARM registe
    [all...]

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