1 /* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator. 2 Copyright (C) 1994 Advanced RISC Machines Ltd. 3 4 This program is free software; you can redistribute it and/or modify 5 it under the terms of the GNU General Public License as published by 6 the Free Software Foundation; either version 3 of the License, or 7 (at your option) any later version. 8 9 This program is distributed in the hope that it will be useful, 10 but WITHOUT ANY WARRANTY; without even the implied warranty of 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 GNU General Public License for more details. 13 14 You should have received a copy of the GNU General Public License 15 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 16 17 #ifndef ARMDEFS_H 18 #define ARMDEFS_H 19 20 #include <stdio.h> 21 #include <stdlib.h> 22 #include <stdint.h> 23 #include <ansidecl.h> 24 25 #define FALSE 0 26 #define TRUE 1 27 #define LOW 0 28 #define HIGH 1 29 #define LOWHIGH 1 30 #define HIGHLOW 2 31 32 typedef uint32_t ARMword; 33 typedef int32_t ARMsword; 34 typedef uint64_t ARMdword; 35 typedef int64_t ARMsdword; 36 typedef struct ARMul_State ARMul_State; 37 38 typedef unsigned ARMul_CPInits (ARMul_State * state); 39 typedef unsigned ARMul_CPExits (ARMul_State * state); 40 typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type, 41 ARMword instr, ARMword value); 42 typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type, 43 ARMword instr, ARMword * value); 44 typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type, 45 ARMword instr, ARMword * value); 46 typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type, 47 ARMword instr, ARMword value); 48 typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type, 49 ARMword instr); 50 typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg, 51 ARMword * value); 52 typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg, 53 ARMword value); 54 55 typedef double ARMdval; /* FIXME: Must be a 64-bit floating point type. */ 56 typedef float ARMfval; /* FIXME: Must be a 32-bit floating point type. */ 57 58 typedef union 59 { 60 ARMword uword[2]; 61 ARMsword sword[2]; 62 ARMfval fval[2]; 63 ARMdword dword; 64 ARMdval dval; 65 } ARM_VFP_reg; 66 67 #define VFP_fval(N) (state->VFP_Reg[(N)>> 1].fval[(N) & 1]) 68 #define VFP_uword(N) (state->VFP_Reg[(N)>> 1].uword[(N) & 1]) 69 #define VFP_sword(N) (state->VFP_Reg[(N)>> 1].sword[(N) & 1]) 70 71 #define VFP_dval(N) (state->VFP_Reg[(N)].dval) 72 #define VFP_dword(N) (state->VFP_Reg[(N)].dword) 73 74 struct ARMul_State 75 { 76 ARMword Emulate; /* to start and stop emulation */ 77 unsigned EndCondition; /* reason for stopping */ 78 ARMword Reg[16]; /* the current register file */ 79 ARMword RegBank[7][16]; /* all the registers */ 80 /* 40 bit accumulator. We always keep this 64 bits wide, 81 and move only 40 bits out of it in an MRA insn. */ 82 ARMdword Accumulator; 83 ARMword Cpsr; /* the current psr */ 84 ARMword Spsr[7]; /* the exception psr's */ 85 ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */ 86 ARMword SFlag; 87 #ifdef MODET 88 ARMword TFlag; /* Thumb state */ 89 #endif 90 ARMword Bank; /* the current register bank */ 91 ARMword Mode; /* the current mode */ 92 ARMword instr, pc, temp; /* saved register state */ 93 ARMword loaded, decoded; /* saved pipeline state */ 94 unsigned long NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */ 95 unsigned long NumInstrs; /* the number of instructions executed */ 96 unsigned NextInstr; 97 unsigned VectorCatch; /* caught exception mask */ 98 unsigned CallDebug; /* set to call the debugger */ 99 unsigned CanWatch; /* set by memory interface if its willing to suffer the 100 overhead of checking for watchpoints on each memory 101 access */ 102 unsigned MemReadDebug, MemWriteDebug; 103 unsigned long StopHandle; 104 105 unsigned char *MemDataPtr; /* admin data */ 106 unsigned char *MemInPtr; /* the Data In bus */ 107 unsigned char *MemOutPtr; /* the Data Out bus (which you may not need */ 108 unsigned char *MemSparePtr; /* extra space */ 109 ARMword MemSize; 110 111 unsigned char *OSptr; /* OS Handle */ 112 char *CommandLine; /* Command Line from ARMsd */ 113 114 ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */ 115 ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */ 116 ARMul_LDCs *LDC[16]; /* LDC instruction */ 117 ARMul_STCs *STC[16]; /* STC instruction */ 118 ARMul_MRCs *MRC[16]; /* MRC instruction */ 119 ARMul_MCRs *MCR[16]; /* MCR instruction */ 120 ARMul_CDPs *CDP[16]; /* CDP instruction */ 121 ARMul_CPReads *CPRead[16]; /* Read CP register */ 122 ARMul_CPWrites *CPWrite[16]; /* Write CP register */ 123 unsigned char *CPData[16]; /* Coprocessor data */ 124 unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */ 125 unsigned long LastTime; /* Value of last call to ARMul_Time() */ 126 ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 127 3 set */ 128 129 unsigned EventSet; /* the number of events in the queue */ 130 unsigned long Now; /* time to the nearest cycle */ 131 struct EventNode **EventPtr; /* the event list */ 132 133 unsigned Exception; /* enable the next four values */ 134 unsigned Debug; /* show instructions as they are executed */ 135 unsigned NresetSig; /* reset the processor */ 136 unsigned NfiqSig; 137 unsigned NirqSig; 138 139 unsigned abortSig; 140 unsigned NtransSig; 141 unsigned bigendSig; 142 unsigned prog32Sig; 143 unsigned data32Sig; 144 unsigned lateabtSig; 145 ARMword Vector; /* synthesize aborts in cycle modes */ 146 ARMword Aborted; /* sticky flag for aborts */ 147 ARMword Reseted; /* sticky flag for Reset */ 148 ARMword Inted, LastInted; /* sticky flags for interrupts */ 149 ARMword Base; /* extra hand for base writeback */ 150 ARMword AbortAddr; /* to keep track of Prefetch aborts */ 151 152 const struct Dbg_HostosInterface *hostif; 153 154 unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */ 155 unsigned is_v5; /* Are we emulating a v5 architecture ? */ 156 unsigned is_v5e; /* Are we emulating a v5e architecture ? */ 157 unsigned is_v6; /* Are we emulating a v6 architecture ? */ 158 unsigned is_XScale; /* Are we emulating an XScale architecture ? */ 159 unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */ 160 unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */ 161 unsigned verbose; /* Print various messages like the banner */ 162 163 ARM_VFP_reg VFP_Reg[32]; /* Advanced SIMD registers. */ 164 ARMword FPSCR; /* Floating Point Status Register. */ 165 }; 166 167 /***************************************************************************\ 168 * Properties of ARM we know about * 169 \***************************************************************************/ 170 171 /* The bitflags */ 172 #define ARM_Fix26_Prop 0x01 173 #define ARM_Nexec_Prop 0x02 174 #define ARM_Debug_Prop 0x10 175 #define ARM_Isync_Prop ARM_Debug_Prop 176 #define ARM_Lock_Prop 0x20 177 #define ARM_v4_Prop 0x40 178 #define ARM_v5_Prop 0x80 179 #define ARM_v5e_Prop 0x100 180 #define ARM_XScale_Prop 0x200 181 #define ARM_ep9312_Prop 0x400 182 #define ARM_iWMMXt_Prop 0x800 183 #define ARM_v6_Prop 0x1000 184 185 /***************************************************************************\ 186 * Macros to extract instruction fields * 187 \***************************************************************************/ 188 189 #undef BIT /* common/sim-bits.h conflict :( */ 190 #define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */ 191 #define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */ 192 #define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */ 193 194 /***************************************************************************\ 195 * The hardware vector addresses * 196 \***************************************************************************/ 197 198 #define ARMResetV 0L 199 #define ARMUndefinedInstrV 4L 200 #define ARMSWIV 8L 201 #define ARMPrefetchAbortV 12L 202 #define ARMDataAbortV 16L 203 #define ARMAddrExceptnV 20L 204 #define ARMIRQV 24L 205 #define ARMFIQV 28L 206 #define ARMErrorV 32L /* This is an offset, not an address ! */ 207 208 #define ARMul_ResetV ARMResetV 209 #define ARMul_UndefinedInstrV ARMUndefinedInstrV 210 #define ARMul_SWIV ARMSWIV 211 #define ARMul_PrefetchAbortV ARMPrefetchAbortV 212 #define ARMul_DataAbortV ARMDataAbortV 213 #define ARMul_AddrExceptnV ARMAddrExceptnV 214 #define ARMul_IRQV ARMIRQV 215 #define ARMul_FIQV ARMFIQV 216 217 /***************************************************************************\ 218 * Mode and Bank Constants * 219 \***************************************************************************/ 220 221 #define USER26MODE 0L 222 #define FIQ26MODE 1L 223 #define IRQ26MODE 2L 224 #define SVC26MODE 3L 225 #define USER32MODE 16L 226 #define FIQ32MODE 17L 227 #define IRQ32MODE 18L 228 #define SVC32MODE 19L 229 #define ABORT32MODE 23L 230 #define UNDEF32MODE 27L 231 #define SYSTEMMODE 31L 232 233 #define ARM32BITMODE (state->Mode > 3) 234 #define ARM26BITMODE (state->Mode <= 3) 235 #define ARMMODE (state->Mode) 236 #define ARMul_MODEBITS 0x1fL 237 #define ARMul_MODE32BIT ARM32BITMODE 238 #define ARMul_MODE26BIT ARM26BITMODE 239 240 #define USERBANK 0 241 #define FIQBANK 1 242 #define IRQBANK 2 243 #define SVCBANK 3 244 #define ABORTBANK 4 245 #define UNDEFBANK 5 246 #define DUMMYBANK 6 247 #define SYSTEMBANK USERBANK 248 249 #define BANK_CAN_ACCESS_SPSR(bank) \ 250 ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK) 251 252 /***************************************************************************\ 253 * Definitons of things in the emulator * 254 \***************************************************************************/ 255 256 extern void ARMul_EmulateInit (void); 257 extern ARMul_State *ARMul_NewState (void); 258 extern void ARMul_Reset (ARMul_State * state); 259 extern ARMword ARMul_DoProg (ARMul_State * state); 260 extern ARMword ARMul_DoInstr (ARMul_State * state); 261 262 /***************************************************************************\ 263 * Definitons of things for event handling * 264 \***************************************************************************/ 265 266 extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay, 267 unsigned (*func) ()); 268 extern void ARMul_EnvokeEvent (ARMul_State * state); 269 extern unsigned long ARMul_Time (ARMul_State * state); 270 271 /***************************************************************************\ 272 * Useful support routines * 273 \***************************************************************************/ 274 275 extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode, 276 unsigned reg); 277 extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, 278 ARMword value); 279 extern ARMword ARMul_GetPC (ARMul_State * state); 280 extern ARMword ARMul_GetNextPC (ARMul_State * state); 281 extern void ARMul_SetPC (ARMul_State * state, ARMword value); 282 extern ARMword ARMul_GetR15 (ARMul_State * state); 283 extern void ARMul_SetR15 (ARMul_State * state, ARMword value); 284 285 extern ARMword ARMul_GetCPSR (ARMul_State * state); 286 extern void ARMul_SetCPSR (ARMul_State * state, ARMword value); 287 extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode); 288 extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value); 289 290 /***************************************************************************\ 291 * Definitons of things to handle aborts * 292 \***************************************************************************/ 293 294 extern void ARMul_Abort (ARMul_State * state, ARMword address); 295 #define ARMul_ABORTWORD 0xefffffff /* SWI -1 */ 296 #define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \ 297 state->AbortAddr = (address & ~3L) 298 #define ARMul_DATAABORT(address) state->abortSig = HIGH ; \ 299 state->Aborted = ARMul_DataAbortV ; 300 #define ARMul_CLEARABORT state->abortSig = LOW 301 302 /***************************************************************************\ 303 * Definitons of things in the memory interface * 304 \***************************************************************************/ 305 306 extern unsigned ARMul_MemoryInit (ARMul_State * state, 307 unsigned long initmemsize); 308 extern void ARMul_MemoryExit (ARMul_State * state); 309 310 extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, 311 ARMword isize); 312 extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, 313 ARMword isize); 314 extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address, 315 ARMword isize); 316 317 extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address); 318 extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address); 319 extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address); 320 extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address); 321 322 extern void ARMul_StoreWordS (ARMul_State * state, ARMword address, 323 ARMword data); 324 extern void ARMul_StoreWordN (ARMul_State * state, ARMword address, 325 ARMword data); 326 extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address, 327 ARMword data); 328 extern void ARMul_StoreByte (ARMul_State * state, ARMword address, 329 ARMword data); 330 331 extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, 332 ARMword data); 333 extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, 334 ARMword data); 335 336 extern void ARMul_Icycles (ARMul_State * state, unsigned number, 337 ARMword address); 338 extern void ARMul_Ccycles (ARMul_State * state, unsigned number, 339 ARMword address); 340 341 extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address); 342 extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address); 343 extern ARMword ARMul_SafeReadByte (ARMul_State * state, ARMword address); 344 extern void ARMul_WriteWord (ARMul_State * state, ARMword address, 345 ARMword data); 346 extern void ARMul_WriteByte (ARMul_State * state, ARMword address, 347 ARMword data); 348 extern void ARMul_SafeWriteByte (ARMul_State * state, ARMword address, 349 ARMword data); 350 351 extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword, 352 ARMword, ARMword, ARMword, ARMword, ARMword, 353 ARMword, ARMword, ARMword); 354 355 /***************************************************************************\ 356 * Definitons of things in the co-processor interface * 357 \***************************************************************************/ 358 359 #define ARMul_FIRST 0 360 #define ARMul_TRANSFER 1 361 #define ARMul_BUSY 2 362 #define ARMul_DATA 3 363 #define ARMul_INTERRUPT 4 364 #define ARMul_DONE 0 365 #define ARMul_CANT 1 366 #define ARMul_INC 3 367 368 #define ARMul_CP13_R0_FIQ 0x1 369 #define ARMul_CP13_R0_IRQ 0x2 370 #define ARMul_CP13_R8_PMUS 0x1 371 372 #define ARMul_CP14_R0_ENABLE 0x0001 373 #define ARMul_CP14_R0_CLKRST 0x0004 374 #define ARMul_CP14_R0_CCD 0x0008 375 #define ARMul_CP14_R0_INTEN0 0x0010 376 #define ARMul_CP14_R0_INTEN1 0x0020 377 #define ARMul_CP14_R0_INTEN2 0x0040 378 #define ARMul_CP14_R0_FLAG0 0x0100 379 #define ARMul_CP14_R0_FLAG1 0x0200 380 #define ARMul_CP14_R0_FLAG2 0x0400 381 #define ARMul_CP14_R10_MOE_IB 0x0004 382 #define ARMul_CP14_R10_MOE_DB 0x0008 383 #define ARMul_CP14_R10_MOE_BT 0x000c 384 #define ARMul_CP15_R1_ENDIAN 0x0080 385 #define ARMul_CP15_R1_ALIGN 0x0002 386 #define ARMul_CP15_R5_X 0x0400 387 #define ARMul_CP15_R5_ST_ALIGN 0x0001 388 #define ARMul_CP15_R5_IMPRE 0x0406 389 #define ARMul_CP15_R5_MMU_EXCPT 0x0400 390 #define ARMul_CP15_DBCON_M 0x0100 391 #define ARMul_CP15_DBCON_E1 0x000c 392 #define ARMul_CP15_DBCON_E0 0x0003 393 394 extern unsigned ARMul_CoProInit (ARMul_State * state); 395 extern void ARMul_CoProExit (ARMul_State * state); 396 extern void ARMul_CoProAttach (ARMul_State * state, unsigned number, 397 ARMul_CPInits * init, ARMul_CPExits * exit, 398 ARMul_LDCs * ldc, ARMul_STCs * stc, 399 ARMul_MRCs * mrc, ARMul_MCRs * mcr, 400 ARMul_CDPs * cdp, 401 ARMul_CPReads * read, ARMul_CPWrites * write); 402 extern void ARMul_CoProDetach (ARMul_State * state, unsigned number); 403 extern void XScale_check_memacc (ARMul_State * state, ARMword * address, 404 int store); 405 extern void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far); 406 extern int XScale_debug_moe (ARMul_State * state, int moe); 407 408 /***************************************************************************\ 409 * Definitons of things in the host environment * 410 \***************************************************************************/ 411 412 extern unsigned ARMul_OSInit (ARMul_State * state); 413 extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number); 414 415 /***************************************************************************\ 416 * Host-dependent stuff * 417 \***************************************************************************/ 418 419 extern void ARMul_UndefInstr (ARMul_State *, ARMword); 420 extern void ARMul_FixCPSR (ARMul_State *, ARMword, ARMword); 421 extern void ARMul_FixSPSR (ARMul_State *, ARMword, ARMword); 422 extern void ARMul_ConsolePrint (ARMul_State *, const char *, ...) 423 ATTRIBUTE_PRINTF (2, 3); 424 extern void ARMul_SelectProcessor (ARMul_State *, unsigned); 425 426 #endif 427
Indexes created Sun Jun 07 00:24:08 UTC 2026