Home | History | Annotate | Line # | Download | only in mpc5200 
      1 /*	$NetBSD: mpc5200_atareg.h,v 1.1 2026/06/27 13:28:35 rkujawa Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2026 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Radoslaw Kujawa and Robert Swindells.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _POWERPC_MPC5200_MPC5200_ATAREG_H_
     33 #define _POWERPC_MPC5200_MPC5200_ATAREG_H_
     34 
     35 /*
     36  * Register map of the MPC5200B on-chip ATA Controller.
     37  */
     38 
     39 /* Host registers (32-bit). */
     40 #define	ATA_CONFIG	0x00	/* ATA host configuration		*/
     41 #define	ATA_HOST_STATUS	0x04	/* ATA host controller status		*/
     42 #define	ATA_PIO1	0x08	/* PIO timing 1 (t0, t2_8, t2_16)	*/
     43 #define	ATA_PIO2	0x0c	/* PIO timing 2 (t4, t1, ta)		*/
     44 #define	ATA_DMA1	0x10	/* multiword DMA timing 1		*/
     45 #define	ATA_DMA2	0x14	/* multiword DMA timing 2		*/
     46 #define	ATA_UDMA1	0x18	/* ultra DMA timing 1			*/
     47 #define	ATA_UDMA2	0x1c	/* ultra DMA timing 2			*/
     48 #define	ATA_UDMA3	0x20	/* ultra DMA timing 3			*/
     49 #define	ATA_UDMA4	0x24	/* ultra DMA timing 4			*/
     50 #define	ATA_UDMA5	0x28	/* ultra DMA timing 5			*/
     51 
     52 /* Taskfile (drive) registers. */
     53 #define	ATA_DRIVE_CTRL	0x5c	/* device control (W) / alt status (R)	*/
     54 #define	ATA_DRIVE_BASE	0x60	/* data, error/feature, ... command	*/
     55 #define	ATA_DRIVE_STRIDE   4	/* 32-bit cell per taskfile register	*/
     56 #define	ATA_REG_SIZE	0x80	/* covers host regs + taskfile (0x00..0x7f) */
     57 
     58 /*
     59  * ATA host configuration register bits
     60  */
     61 #define	ATA_CONFIG_SMR	0x80000000	/* state machine reset (bit 0)	*/
     62 #define	ATA_CONFIG_FR	0x40000000	/* FIFO reset (bit 1)		*/
     63 #define	ATA_CONFIG_IE	0x02000000	/* PIO drive interrupt enable (6) */
     64 #define	ATA_CONFIG_IORDY 0x01000000	/* honor IORDY, needed PIO >=3 (7) */
     65 
     66 /* ATA host status register bits */
     67 #define	ATA_HOST_STATUS_TIP	0x80000000	/* transaction in progress */
     68 #define	ATA_HOST_STATUS_UREP	0x40000000	/* UDMA read extended pause */
     69 #define	ATA_HOST_STATUS_RERR	0x02000000	/* read of unimpl. register */
     70 #define	ATA_HOST_STATUS_WERR	0x01000000	/* write of unimpl. register */
     71 
     72 #endif /* _POWERPC_MPC5200_MPC5200_ATAREG_H_ */
     73