| /src/external/gpl3/binutils/dist/opcodes/ |
| tic54x-opc.c | 117 #define CC1 0x40
133 { "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ },
134 { "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ },
135 { "alt", CC1|CCLT }, { "ALT", CC1|CCLT },
136 { "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ },
137 { "agt", CC1|CCGT }, { "AGT", CC1|CCGT }
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| tic54x-opc.c | 117 #define CC1 0x40
133 { "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ },
134 { "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ },
135 { "alt", CC1|CCLT }, { "ALT", CC1|CCLT },
136 { "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ },
137 { "agt", CC1|CCGT }, { "AGT", CC1|CCGT }
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| tic54x-opc.c | 117 #define CC1 0x40
133 { "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ },
134 { "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ },
135 { "alt", CC1|CCLT }, { "ALT", CC1|CCLT },
136 { "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ },
137 { "agt", CC1|CCGT }, { "AGT", CC1|CCGT }
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| tic54x-opc.c | 117 #define CC1 0x40
133 { "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ },
134 { "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ },
135 { "alt", CC1|CCLT }, { "ALT", CC1|CCLT },
136 { "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ },
137 { "agt", CC1|CCGT }, { "AGT", CC1|CCGT }
[all...] |
| /src/external/gpl3/gcc/dist/libgcc/config/avr/ |
| lib1funcs-fixed.S | 522 #define CC1 1
601 add CC0,A0 $ adc CC1,A1 $ adc CC2,A2 $ adc CC3,A3
622 add B3,B2 $ adc CC0,A0 $ adc CC1,A1 $ adc CC2,A2 $ adc CC3,A3
674 #undef CC1
|
| lib1funcs.S | 260 #define CC1 21
315 clr CC1
320 adc CC1, B1
343 mov C1, CC1
356 #undef CC1
371 #define CC1 CC0+1
436 in r26, __SP_L__ ; safe to use X, as it is CC0/CC1
455 clr CC1
460 add CC0,B0 $ adc CC1,B1 $ adc CC2,B2 $ adc CC3,B3
500 #undef CC1
[all...] |
| /src/external/gpl3/gcc.old/dist/libgcc/config/avr/ |
| lib1funcs-fixed.S | 522 #define CC1 1
601 add CC0,A0 $ adc CC1,A1 $ adc CC2,A2 $ adc CC3,A3
622 add B3,B2 $ adc CC0,A0 $ adc CC1,A1 $ adc CC2,A2 $ adc CC3,A3
674 #undef CC1
|
| lib1funcs.S | 255 #define CC1 21
310 clr CC1
315 adc CC1, B1
338 mov C1, CC1
351 #undef CC1
366 #define CC1 CC0+1
431 in r26, __SP_L__ ; safe to use X, as it is CC0/CC1
450 clr CC1
455 add CC0,B0 $ adc CC1,B1 $ adc CC2,B2 $ adc CC3,B3
495 #undef CC1
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 471 Constant *CC1 = ConstantExpr::getFMul(C, C1);
472 if (CC1->isNormalFP())
473 return BinaryOperator::CreateFDivFMF(CC1, X, &I);
493 Constant *CC1 = ConstantExpr::getFMul(C, C1);
495 return BinaryOperator::CreateFAddFMF(XC, CC1, &I);
499 Constant *CC1 = ConstantExpr::getFMul(C, C1);
501 return BinaryOperator::CreateFSubFMF(CC1, XC, &I);
|
| /src/external/gpl3/gcc.old/dist/gcc/config/s390/ |
| s390.cc | 1494 CC1 and CC2 for mixed selected bits (TMxx), it is false
1516 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
1986 const int CC1 = 1 << 2;
2004 case NE: return CC1 | CC2 | CC3;
2012 case EQ: return CC1;
2022 case NE: return CC0 | CC1 | CC3;
2031 case NE: return CC0 | CC1 | CC2;
2040 case NE: return CC1 | CC3;
2049 case GEU: return CC0 | CC1; /* no carry */
2057 case GTU: return CC0 | CC1; /* borrow *
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/s390/ |
| s390.cc | 1550 CC1 and CC2 for mixed selected bits (TMxx), it is false
1572 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
2133 const int CC1 = 1 << 2;
2151 case NE: return CC1 | CC2 | CC3;
2159 case EQ: return CC1;
2169 case NE: return CC0 | CC1 | CC3;
2178 case NE: return CC0 | CC1 | CC2;
2187 case NE: return CC1 | CC3;
2196 case GEU: return CC0 | CC1; /* no carry */
2204 case GTU: return CC0 | CC1; /* borrow *
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 4971 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
4973 if (LR == RR && CC0 == CC1 && IsInteger) {
4978 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
4980 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1;
4982 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero;
4984 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
4993 return DAG.getSetCC(DL, VT, Or, LR, CC1);
4997 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
4999 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
5001 bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 6708 AArch64CC::CondCode CC1, CC2;
6709 changeFPCCToAArch64CC(CC, CC1, CC2);
6710 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
6935 AArch64CC::CondCode CC1, CC2;
6936 changeFPCCToAArch64CC(CC, CC1, CC2);
6939 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, LHS.getValueType()), CC1,
6941 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
6954 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
7130 AArch64CC::CondCode CC1, CC2;
7131 changeFPCCToAArch64CC(CC, CC1, CC2)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 5049 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5068 !((isGTorGE(CC1) && isLTorLE(CC2)) || (isLTorLE(CC1) && isGTorGE(CC2))))
5082 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
|
