1 /* $NetBSD: cg4.c,v 1.44 2024/12/21 17:40:11 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: @(#)cgthree.c 8.2 (Berkeley) 10/30/93 41 */ 42 43 /* 44 * color display (cg4) driver. 45 * 46 * Credits, history: 47 * Gordon Ross created this driver based on the cg3 driver from 48 * the sparc port as distributed in BSD 4.4 Lite, but included 49 * support for only the "type B" adapter (Brooktree DACs). 50 * Ezra Story added support for the "type A" (AMD DACs). 51 * 52 * Todo: 53 * Make this driver handle video interrupts. 54 * Defer colormap updates to vertical retrace interrupts. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: cg4.c,v 1.44 2024/12/21 17:40:11 tsutsui Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/conf.h> 63 #include <sys/device.h> 64 #include <sys/ioctl.h> 65 #include <sys/kmem.h> 66 #include <sys/mman.h> 67 #include <sys/proc.h> 68 #include <sys/tty.h> 69 70 #include <uvm/uvm_extern.h> 71 72 #include <machine/autoconf.h> 73 #include <machine/cpu.h> 74 #include <dev/sun/fbio.h> 75 #include <machine/idprom.h> 76 #include <machine/pmap.h> 77 78 #include <sun3/dev/fbvar.h> 79 #include <sun3/dev/btreg.h> 80 #include <sun3/dev/cg4reg.h> 81 #include <sun3/dev/p4reg.h> 82 83 #include "ioconf.h" 84 85 union bt_cmap_u { 86 uint8_t btcm_char[256 * 3]; /* raw data */ 87 uint8_t btcm_rgb[256][3]; /* 256 R/G/B entries */ 88 u_int btcm_int[256 * 3 / 4]; /* the way the chip gets loaded */ 89 }; 90 91 #define CG4_TYPE_A 0 /* AMD DACs */ 92 #define CG4_TYPE_B 1 /* Brooktree DACs */ 93 94 #define CG4_MMAP_SIZE (CG4_OVERLAY_SIZE + CG4_ENABLE_SIZE + CG4_PIXMAP_SIZE) 95 96 #define CMAP_SIZE 256 97 struct soft_cmap { 98 uint8_t r[CMAP_SIZE]; 99 uint8_t g[CMAP_SIZE]; 100 uint8_t b[CMAP_SIZE]; 101 }; 102 103 /* per-display variables */ 104 struct cg4_softc { 105 device_t sc_dev; /* base device */ 106 struct fbdevice sc_fb; /* frame buffer device */ 107 int sc_cg4type; /* A or B */ 108 int sc_pa_overlay; /* phys. addr. of overlay plane */ 109 int sc_pa_enable; /* phys. addr. of enable plane */ 110 int sc_pa_pixmap; /* phys. addr. of color plane */ 111 int sc_video_on; /* zero if blanked */ 112 void *sc_va_cmap; /* Colormap h/w (mapped KVA) */ 113 void *sc_btcm; /* Soft cmap, Brooktree format */ 114 void (*sc_ldcmap)(struct cg4_softc *); 115 struct soft_cmap sc_cmap; /* Soft cmap, user format */ 116 }; 117 118 /* autoconfiguration driver */ 119 static int cg4match(device_t, cfdata_t, void *); 120 static void cg4attach(device_t, device_t, void *); 121 122 CFATTACH_DECL_NEW(cgfour, sizeof(struct cg4_softc), 123 cg4match, cg4attach, NULL, NULL); 124 125 static dev_type_open(cg4open); 126 static dev_type_ioctl(cg4ioctl); 127 static dev_type_mmap(cg4mmap); 128 129 const struct cdevsw cgfour_cdevsw = { 130 .d_open = cg4open, 131 .d_close = nullclose, 132 .d_read = noread, 133 .d_write = nowrite, 134 .d_ioctl = cg4ioctl, 135 .d_stop = nostop, 136 .d_tty = notty, 137 .d_poll = nopoll, 138 .d_mmap = cg4mmap, 139 .d_kqfilter = nokqfilter, 140 .d_discard = nodiscard, 141 .d_flag = 0 142 }; 143 144 static int cg4gattr (struct fbdevice *, void *); 145 static int cg4gvideo (struct fbdevice *, void *); 146 static int cg4svideo (struct fbdevice *, void *); 147 static int cg4getcmap(struct fbdevice *, void *); 148 static int cg4putcmap(struct fbdevice *, void *); 149 150 #ifdef _SUN3_ 151 static void cg4a_init (struct cg4_softc *); 152 static void cg4a_ldcmap(struct cg4_softc *); 153 #endif /* SUN3 */ 154 155 static void cg4b_init (struct cg4_softc *); 156 static void cg4b_ldcmap(struct cg4_softc *); 157 158 static struct fbdriver cg4_fbdriver = { 159 cg4open, nullclose, cg4mmap, nokqfilter, cg4gattr, 160 cg4gvideo, cg4svideo, 161 cg4getcmap, cg4putcmap }; 162 163 /* 164 * Match a cg4. 165 */ 166 static int 167 cg4match(device_t parent, cfdata_t cf, void *args) 168 { 169 struct confargs *ca = args; 170 int mid, p4id, peekval, tmp; 171 void *p4reg; 172 173 /* No default address support. */ 174 if (ca->ca_paddr == -1) 175 return 0; 176 177 /* 178 * Slight hack here: The low four bits of the 179 * config flags, if set, restrict the match to 180 * that machine "implementation" only. 181 */ 182 mid = cf->cf_flags & IDM_IMPL_MASK; 183 if (mid && (mid != (cpu_machine_id & IDM_IMPL_MASK))) 184 return 0; 185 186 /* 187 * The config flag 0x10 if set means we are 188 * looking for a Type A board (3/110). 189 */ 190 if (cf->cf_flags & 0x10) { 191 #ifdef _SUN3_ 192 /* Type A: Check for AMD RAMDACs in control space. */ 193 if (bus_peek(BUS_OBIO, CG4A_OBIO_CMAP, 1) == -1) 194 return 0; 195 /* Check for the overlay plane. */ 196 tmp = ca->ca_paddr + CG4A_OFF_OVERLAY; 197 if (bus_peek(ca->ca_bustype, tmp, 1) == -1) 198 return 0; 199 /* OK, it looks like a Type A. */ 200 return 1; 201 #else /* SUN3 */ 202 /* Only the Sun3/110 ever has a type A. */ 203 return 0; 204 #endif /* SUN3 */ 205 } 206 207 /* 208 * From here on, it is a type B or nothing. 209 * The config flag 0x20 if set means there 210 * is no P4 register. (bus error) 211 */ 212 if ((cf->cf_flags & 0x20) == 0) { 213 p4reg = bus_tmapin(ca->ca_bustype, ca->ca_paddr); 214 peekval = peek_long(p4reg); 215 p4id = (peekval == -1) ? 216 P4_NOTFOUND : fb_pfour_id(p4reg); 217 bus_tmapout(p4reg); 218 if (peekval == -1) 219 return (0); 220 if (p4id != P4_ID_COLOR8P1) { 221 #ifdef DEBUG 222 aprint_debug("cgfour at 0x%lx match p4id=0x%x fails\n", 223 ca->ca_paddr, p4id & 0xFF); 224 #endif 225 return 0; 226 } 227 } 228 229 /* 230 * Check for CMAP hardware and overlay plane. 231 */ 232 tmp = ca->ca_paddr + CG4B_OFF_CMAP; 233 if (bus_peek(ca->ca_bustype, tmp, 4) == -1) 234 return 0; 235 tmp = ca->ca_paddr + CG4B_OFF_OVERLAY; 236 if (bus_peek(ca->ca_bustype, tmp, 1) == -1) 237 return 0; 238 239 return 1; 240 } 241 242 /* 243 * Attach a display. We need to notice if it is the console, too. 244 */ 245 static void 246 cg4attach(device_t parent, device_t self, void *args) 247 { 248 struct cg4_softc *sc = device_private(self); 249 struct fbdevice *fb = &sc->sc_fb; 250 struct confargs *ca = args; 251 struct fbtype *fbt; 252 int tmp; 253 254 sc->sc_dev = self; 255 256 fbt = &fb->fb_fbtype; 257 fbt->fb_type = FBTYPE_SUN4COLOR; 258 fbt->fb_width = 1152; /* default - see below */ 259 fbt->fb_height = 900; /* default - see below */ 260 fbt->fb_depth = 8; 261 fbt->fb_cmsize = 256; 262 fbt->fb_size = CG4_MMAP_SIZE; 263 fb->fb_driver = &cg4_fbdriver; 264 fb->fb_private = sc; 265 fb->fb_name = device_xname(self); 266 fb->fb_flags = device_cfdata(self)->cf_flags; 267 268 /* 269 * The config flag 0x10 if set means we are 270 * attaching a Type A (3/110) which has the 271 * AMD RAMDACs in control space, and no P4. 272 */ 273 if (fb->fb_flags & 0x10) { 274 #ifdef _SUN3_ 275 sc->sc_cg4type = CG4_TYPE_A; 276 sc->sc_ldcmap = cg4a_ldcmap; 277 sc->sc_pa_overlay = ca->ca_paddr + CG4A_OFF_OVERLAY; 278 sc->sc_pa_enable = ca->ca_paddr + CG4A_OFF_ENABLE; 279 sc->sc_pa_pixmap = ca->ca_paddr + CG4A_OFF_PIXMAP; 280 sc->sc_va_cmap = bus_mapin(BUS_OBIO, CG4A_OBIO_CMAP, 281 sizeof(struct amd_regs)); 282 cg4a_init(sc); 283 #else /* SUN3 */ 284 panic("cgfour flags 0x10"); 285 #endif /* SUN3 */ 286 } else { 287 sc->sc_cg4type = CG4_TYPE_B; 288 sc->sc_ldcmap = cg4b_ldcmap; 289 sc->sc_pa_overlay = ca->ca_paddr + CG4B_OFF_OVERLAY; 290 sc->sc_pa_enable = ca->ca_paddr + CG4B_OFF_ENABLE; 291 sc->sc_pa_pixmap = ca->ca_paddr + CG4B_OFF_PIXMAP; 292 tmp = ca->ca_paddr + CG4B_OFF_CMAP; 293 sc->sc_va_cmap = bus_mapin(ca->ca_bustype, tmp, 294 sizeof(struct bt_regs)); 295 cg4b_init(sc); 296 } 297 298 if ((fb->fb_flags & 0x20) == 0) { 299 /* It is supposed to have a P4 register. */ 300 fb->fb_pfour = bus_mapin(ca->ca_bustype, ca->ca_paddr, 4); 301 } 302 303 /* 304 * Determine width and height as follows: 305 * If it has a P4 register, use that; 306 * else if unit==0, use the EEPROM size, 307 * else make our best guess. 308 */ 309 if (fb->fb_pfour) 310 fb_pfour_setsize(fb); 311 /* XXX device_unit() abuse */ 312 else if (device_unit(self) == 0) 313 fb_eeprom_setsize(fb); 314 else { 315 /* Guess based on machine ID. */ 316 switch (cpu_machine_id) { 317 default: 318 /* Leave the defaults set above. */ 319 break; 320 } 321 } 322 aprint_normal(" (%dx%d)\n", fbt->fb_width, fbt->fb_height); 323 324 /* 325 * Make sure video is on. This driver uses a 326 * black colormap to blank the screen, so if 327 * there is any global enable, set it here. 328 */ 329 tmp = 1; 330 cg4svideo(fb, &tmp); 331 if (fb->fb_pfour) 332 fb_pfour_set_video(fb, 1); 333 else 334 enable_video(1); 335 336 /* Let /dev/fb know we are here. */ 337 fb_attach(fb, 4); 338 } 339 340 static int 341 cg4open(dev_t dev, int flags, int mode, struct lwp *l) 342 { 343 struct cg4_softc *sc; 344 int unit = minor(dev); 345 346 sc = device_lookup_private(&cgfour_cd, unit); 347 if (sc == NULL) 348 return ENXIO; 349 return 0; 350 } 351 352 static int 353 cg4ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 354 { 355 struct cg4_softc *sc = device_lookup_private(&cgfour_cd, minor(dev)); 356 357 return fbioctlfb(&sc->sc_fb, cmd, data); 358 } 359 360 /* 361 * Return the address that would map the given device at the given 362 * offset, allowing for the given protection, or return -1 for error. 363 * 364 * X11 expects its mmap'd region to look like this: 365 * 128k overlay data memory 366 * 128k overlay enable bitmap 367 * 1024k color memory 368 * 369 * The hardware looks completely different. 370 */ 371 static paddr_t 372 cg4mmap(dev_t dev, off_t off, int prot) 373 { 374 struct cg4_softc *sc = device_lookup_private(&cgfour_cd, minor(dev)); 375 int physbase; 376 377 if (off & PGOFSET) 378 panic("%s: bad offset", __func__); 379 380 if ((off < 0) || (off >= CG4_MMAP_SIZE)) 381 return -1; 382 383 if (off < 0x40000) { 384 if (off < 0x20000) { 385 physbase = sc->sc_pa_overlay; 386 } else { 387 /* enable plane */ 388 off -= 0x20000; 389 physbase = sc->sc_pa_enable; 390 } 391 } else { 392 /* pixel map */ 393 off -= 0x40000; 394 physbase = sc->sc_pa_pixmap; 395 } 396 397 /* 398 * I turned on PMAP_NC here to disable the cache as I was 399 * getting horribly broken behaviour without it. 400 */ 401 return (physbase + off) | PMAP_NC; 402 } 403 404 /* 405 * Internal ioctl functions. 406 */ 407 408 /* FBIOGATTR: */ 409 static int 410 cg4gattr(struct fbdevice *fb, void *data) 411 { 412 struct fbgattr *fba = data; 413 414 fba->real_type = fb->fb_fbtype.fb_type; 415 fba->owner = 0; /* XXX - TIOCCONS stuff? */ 416 fba->fbtype = fb->fb_fbtype; 417 fba->sattr.flags = 0; 418 fba->sattr.emu_type = fb->fb_fbtype.fb_type; 419 fba->sattr.dev_specific[0] = -1; 420 fba->emu_types[0] = fb->fb_fbtype.fb_type; 421 fba->emu_types[1] = -1; 422 return 0; 423 } 424 425 /* FBIOGVIDEO: */ 426 static int 427 cg4gvideo(struct fbdevice *fb, void *data) 428 { 429 struct cg4_softc *sc = fb->fb_private; 430 int *on = data; 431 432 *on = sc->sc_video_on; 433 return 0; 434 } 435 436 /* FBIOSVIDEO: */ 437 static int 438 cg4svideo(struct fbdevice *fb, void *data) 439 { 440 struct cg4_softc *sc = fb->fb_private; 441 int *on = data; 442 443 if (sc->sc_video_on == *on) 444 return 0; 445 sc->sc_video_on = *on; 446 447 (*sc->sc_ldcmap)(sc); 448 return 0; 449 } 450 451 /* 452 * FBIOGETCMAP: 453 * Copy current colormap out to user space. 454 */ 455 static int 456 cg4getcmap(struct fbdevice *fb, void *data) 457 { 458 struct cg4_softc *sc = fb->fb_private; 459 struct soft_cmap *cm = &sc->sc_cmap; 460 struct fbcmap *fbcm = data; 461 u_int start, count; 462 int error; 463 464 start = fbcm->index; 465 count = fbcm->count; 466 if (start >= CMAP_SIZE || count > CMAP_SIZE - start) 467 return EINVAL; 468 469 if ((error = copyout(&cm->r[start], fbcm->red, count)) != 0) 470 return error; 471 472 if ((error = copyout(&cm->g[start], fbcm->green, count)) != 0) 473 return error; 474 475 if ((error = copyout(&cm->b[start], fbcm->blue, count)) != 0) 476 return error; 477 478 return 0; 479 } 480 481 /* 482 * FBIOPUTCMAP: 483 * Copy new colormap from user space and load. 484 */ 485 static int 486 cg4putcmap(struct fbdevice *fb, void *data) 487 { 488 struct cg4_softc *sc = fb->fb_private; 489 struct soft_cmap *cm = &sc->sc_cmap; 490 struct fbcmap *fbcm = data; 491 u_int start, count; 492 int error; 493 494 start = fbcm->index; 495 count = fbcm->count; 496 if (start >= CMAP_SIZE || count > CMAP_SIZE - start) 497 return EINVAL; 498 499 if ((error = copyin(fbcm->red, &cm->r[start], count)) != 0) 500 return error; 501 502 if ((error = copyin(fbcm->green, &cm->g[start], count)) != 0) 503 return error; 504 505 if ((error = copyin(fbcm->blue, &cm->b[start], count)) != 0) 506 return error; 507 508 (*sc->sc_ldcmap)(sc); 509 return 0; 510 } 511 512 /**************************************************************** 513 * Routines for the "Type A" hardware 514 ****************************************************************/ 515 #ifdef _SUN3_ 516 517 static void 518 cg4a_init(struct cg4_softc *sc) 519 { 520 volatile struct amd_regs *ar = sc->sc_va_cmap; 521 struct soft_cmap *cm = &sc->sc_cmap; 522 int i; 523 524 /* Grab initial (current) color map. */ 525 for(i = 0; i < 256; i++) { 526 cm->r[i] = ar->r[i]; 527 cm->g[i] = ar->g[i]; 528 cm->b[i] = ar->b[i]; 529 } 530 } 531 532 static void 533 cg4a_ldcmap(struct cg4_softc *sc) 534 { 535 volatile struct amd_regs *ar = sc->sc_va_cmap; 536 struct soft_cmap *cm = &sc->sc_cmap; 537 int i; 538 539 /* 540 * Now blast them into the chip! 541 * XXX Should use retrace interrupt! 542 * Just set a "need load" bit and let the 543 * retrace interrupt handler do the work. 544 */ 545 if (sc->sc_video_on) { 546 /* Update H/W colormap. */ 547 for (i = 0; i < 256; i++) { 548 ar->r[i] = cm->r[i]; 549 ar->g[i] = cm->g[i]; 550 ar->b[i] = cm->b[i]; 551 } 552 } else { 553 /* Clear H/W colormap. */ 554 for (i = 0; i < 256; i++) { 555 ar->r[i] = 0; 556 ar->g[i] = 0; 557 ar->b[i] = 0; 558 } 559 } 560 } 561 #endif /* SUN3 */ 562 563 /**************************************************************** 564 * Routines for the "Type B" hardware 565 ****************************************************************/ 566 567 static void 568 cg4b_init(struct cg4_softc *sc) 569 { 570 volatile struct bt_regs *bt = sc->sc_va_cmap; 571 struct soft_cmap *cm = &sc->sc_cmap; 572 union bt_cmap_u *btcm; 573 int i; 574 575 /* Need a buffer for colormap format translation. */ 576 btcm = kmem_alloc(sizeof(*btcm), KM_SLEEP); 577 sc->sc_btcm = btcm; 578 579 /* 580 * BT458 chip initialization as described in Brooktree's 581 * 1993 Graphics and Imaging Product Databook (DB004-1/93). 582 * 583 * It appears that the 3/60 uses the low byte, and the 3/80 584 * uses the high byte, while both ignore the other bytes. 585 * Writing same value to all bytes works on both. 586 */ 587 bt->bt_addr = 0x04040404; /* select read mask register */ 588 bt->bt_ctrl = ~0; /* all planes on */ 589 bt->bt_addr = 0x05050505; /* select blink mask register */ 590 bt->bt_ctrl = 0; /* all planes non-blinking */ 591 bt->bt_addr = 0x06060606; /* select command register */ 592 bt->bt_ctrl = 0x43434343; /* palette enabled, overlay planes enabled */ 593 bt->bt_addr = 0x07070707; /* select test register */ 594 bt->bt_ctrl = 0; /* not test mode */ 595 596 /* grab initial (current) color map */ 597 bt->bt_addr = 0; 598 #ifdef _SUN3_ 599 /* Sun3/60 wants 32-bit access, packed. */ 600 for (i = 0; i < (256 * 3 / 4); i++) 601 btcm->btcm_int[i] = bt->bt_cmap; 602 #else /* SUN3 */ 603 /* Sun3/80 wants 8-bits in the high byte. */ 604 for (i = 0; i < (256 * 3); i++) 605 btcm->btcm_char[i] = bt->bt_cmap >> 24; 606 #endif /* SUN3 */ 607 608 /* Transpose into H/W cmap into S/W form. */ 609 for (i = 0; i < 256; i++) { 610 cm->r[i] = btcm->btcm_rgb[i][0]; 611 cm->g[i] = btcm->btcm_rgb[i][1]; 612 cm->b[i] = btcm->btcm_rgb[i][2]; 613 } 614 } 615 616 static void 617 cg4b_ldcmap(struct cg4_softc *sc) 618 { 619 volatile struct bt_regs *bt = sc->sc_va_cmap; 620 struct soft_cmap *cm = &sc->sc_cmap; 621 union bt_cmap_u *btcm = sc->sc_btcm; 622 int i; 623 624 /* Transpose S/W cmap into H/W form. */ 625 for (i = 0; i < 256; i++) { 626 btcm->btcm_rgb[i][0] = cm->r[i]; 627 btcm->btcm_rgb[i][1] = cm->g[i]; 628 btcm->btcm_rgb[i][2] = cm->b[i]; 629 } 630 631 /* 632 * Now blast them into the chip! 633 * XXX Should use retrace interrupt! 634 * Just set a "need load" bit and let the 635 * retrace interrupt handler do the work. 636 */ 637 bt->bt_addr = 0; 638 639 #ifdef _SUN3_ 640 /* Sun3/60 wants 32-bit access, packed. */ 641 if (sc->sc_video_on) { 642 /* Update H/W colormap. */ 643 for (i = 0; i < (256 * 3 / 4); i++) 644 bt->bt_cmap = btcm->btcm_int[i]; 645 } else { 646 /* Clear H/W colormap. */ 647 for (i = 0; i < (256 * 3 / 4); i++) 648 bt->bt_cmap = 0; 649 } 650 #else /* SUN3 */ 651 /* Sun3/80 wants 8-bits in the high byte. */ 652 if (sc->sc_video_on) { 653 /* Update H/W colormap. */ 654 for (i = 0; i < (256 * 3); i++) 655 bt->bt_cmap = btcm->btcm_char[i] << 24; 656 } else { 657 /* Clear H/W colormap. */ 658 for (i = 0; i < (256 * 3); i++) 659 bt->bt_cmap = 0; 660 } 661 #endif /* SUN3 */ 662 } 663
Indexes created Sun Sep 28 16:09:52 GMT 2025