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    Searched defs:CHIP_W1_BUS_END (Results 1 - 25 of 46) sorted by relevancy

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  /src/sys/arch/algor/algor/
algor_p4032_bus_locio.c 60 #define CHIP_W1_BUS_END(v) 0xffffffffUL
62 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
algor_p4032_bus_io.c 63 #define CHIP_W1_BUS_END(v) \
algor_p5064_bus_io.c 60 #define CHIP_W1_BUS_END(v) 0x00ffffffUL
algor_p6032_bus_io.c 60 #define CHIP_W1_BUS_END(v) 0x000fffffUL
algor_p6032_bus_mem.c 65 #define CHIP_W1_BUS_END(v) 0x0bffffffUL
  /src/sys/arch/cobalt/dev/
gt_io_space.c 51 #define CHIP_W1_BUS_END(v) 0x02000000UL
gt_mem_space.c 51 #define CHIP_W1_BUS_END(v) 0x14000000UL
  /src/sys/arch/mips/adm5120/
adm5120_obio_space.c 80 #define CHIP_W1_BUS_END(v) 0x1fffffffUL
82 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
adm5120_pciio_space.c 50 #define CHIP_W1_BUS_END(v) ADM5120_BASE_PCI_CONFADDR
52 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
adm5120_pcimem_space.c 50 #define CHIP_W1_BUS_END(v) ADM5120_BASE_PCI_IO
52 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
  /src/sys/arch/mips/alchemy/
au_cpureg_mem.c 51 #define CHIP_W1_BUS_END(v) 0x1fffffffUL
53 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
  /src/sys/arch/mips/atheros/
arbusle.c 48 #define CHIP_W1_BUS_END(v) 0x1fffffffUL
50 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
  /src/sys/arch/cobalt/cobalt/
bus.c 54 #define CHIP_W1_BUS_END(v) 0x10000fffUL
  /src/sys/arch/evbmips/gdium/
gdium_bus_io.c 61 #define CHIP_W1_BUS_END(v) 0x000fffffUL
  /src/sys/arch/evbmips/malta/
malta_bus_io.c 52 #define CHIP_W1_BUS_END(v) MALTA_PCIMEM3_SIZE
55 CHIP_W1_BUS_END(v))
  /src/sys/arch/evbmips/mipssim/
mipssim_bus_io.c 52 #define CHIP_W1_BUS_END(v) (MIPSSIM_ISA_IO_SIZE + MIPSSIM_VIRTIO_IO_SIZE)
54 #define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + CHIP_W1_BUS_END(v))
  /src/sys/arch/mips/rmi/
rmixl_iobus_space.c 65 #define CHIP_W1_BUS_END(v) RMIXL_FLASH_BAR_MASK_MAX
rmixl_obio_eb_space.c 58 #define CHIP_W1_BUS_END(v) (RMIXL_IO_DEV_SIZE - 1)
rmixl_obio_el_space.c 58 #define CHIP_W1_BUS_END(v) (RMIXL_IO_DEV_SIZE - 1)
rmixl_pci_cfg_space.c 59 #define CHIP_W1_BUS_END(v) \
63 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
rmixl_pci_ecfg_space.c 59 #define CHIP_W1_BUS_END(v) \
63 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
rmixl_pci_io_space.c 58 #define CHIP_W1_BUS_END(v) (CHIP_W1_SYS_START(v) + \
61 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
rmixl_pci_mem_space.c 58 #define CHIP_W1_BUS_END(v) (CHIP_W1_SYS_START(v) + \
61 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
  /src/sys/arch/mips/sibyte/pci/
sbbrz_bus_io.c 53 #define CHIP_W1_BUS_END(v) 0x02000000UL
55 #define CHIP_W1_SYS_END(v) (A_PHYS_LDTPCI_IO_MATCH_BYTES + CHIP_W1_BUS_END(v))
sbbrz_bus_mem.c 53 #define CHIP_W1_BUS_END(v) (A_PHYS_LDTPCI_IO_MATCH_BYTES_32 + 0x20000000)
55 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

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