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Searched defs:CHIP_W1_SYS_END (Results 1 - 25 of 46) sorted by relevance

/src/sys/arch/cobalt/dev/
H A D	gt_io_space.c	`53 #define CHIP_W1_SYS_END(v) 0x12000000UL macro`
H A D	gt_mem_space.c	`53 #define CHIP_W1_SYS_END(v) 0x14000000UL macro`
/src/sys/arch/algor/algor/
H A D	algor_p4032_bus_locio.c	`62 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) macro`
H A D	algor_p6032_bus_io.c	`62 #define CHIP_W1_SYS_END(v) ((u_long)BONITO_PCIIO_BASE + 0x000fffffUL) macro`
H A D	algor_p6032_bus_mem.c	`67 #define CHIP_W1_SYS_END(v) ((u_long)BONITO_PCILO_BASE + 0x0bffffffUL) macro`
H A D	algor_p4032_bus_io.c	`66 #define CHIP_W1_SYS_END(v) (P4032_PCIIO + 0x000fffffUL) macro`
/src/sys/arch/mips/adm5120/
H A D	adm5120_obio_space.c	`82 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) macro`
H A D	adm5120_pciio_space.c	`52 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) macro`
H A D	adm5120_pcimem_space.c	`52 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) macro`
/src/sys/arch/mips/alchemy/
H A D	au_cpureg_mem.c	`53 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) macro`
/src/sys/arch/mips/atheros/
H A D	arbusle.c	`50 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) macro`
/src/sys/arch/cobalt/cobalt/
H A D	bus.c	`56 #define CHIP_W1_SYS_END(v) 0x10000fffUL macro`
/src/sys/arch/evbmips/gdium/
H A D	gdium_bus_io.c	`63 #define CHIP_W1_SYS_END(v) ((u_long)BONITO_PCIIO_BASE + 0x000fffffUL) macro`
H A D	gdium_bus_mem.c	`67 #define CHIP_W1_SYS_END(v) ((u_long)BONITO_PCILO_BASE + 0x0bffffffUL) macro`
/src/sys/arch/evbmips/malta/
H A D	malta_bus_io.c	`54 #define CHIP_W1_SYS_END(v) ((u_long)MALTA_PCIMEM3_BASE + \ macro`
/src/sys/arch/evbmips/mipssim/
H A D	mipssim_bus_io.c	`54 #define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + CHIP_W1_BUS_END(v)) macro`
/src/sys/arch/mips/rmi/
H A D	rmixl_iobus_space.c	`67 #define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + RMIXL_FLASH_BAR_MASK_MAX) macro`
H A D	rmixl_obio_eb_space.c	`60 #define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + RMIXL_IO_DEV_SIZE - 1) macro`
H A D	rmixl_obio_el_space.c	`60 #define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + RMIXL_IO_DEV_SIZE - 1) macro`
H A D	rmixl_pci_cfg_space.c	`63 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) macro`
H A D	rmixl_pci_ecfg_space.c	`63 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) macro`
H A D	rmixl_pci_io_space.c	`61 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) macro`
H A D	rmixl_pci_mem_space.c	`61 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) macro`
/src/sys/arch/mips/sibyte/pci/
H A D	sbbrz_bus_io.c	`55 #define CHIP_W1_SYS_END(v) (A_PHYS_LDTPCI_IO_MATCH_BYTES + CHIP_W1_BUS_END(v)) macro`
H A D	sbbrz_bus_mem.c	`55 #define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v) macro`

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