1 /* $NetBSD: mt8135-clk.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2014 MediaTek Inc. 6 * Author: James Liao <jamesjj.liao (at) mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_MT8135_H 10 #define _DT_BINDINGS_CLK_MT8135_H 11 12 /* TOPCKGEN */ 13 14 #define CLK_TOP_DSI0_LNTC_DSICLK 1 15 #define CLK_TOP_HDMITX_CLKDIG_CTS 2 16 #define CLK_TOP_CLKPH_MCK 3 17 #define CLK_TOP_CPUM_TCK_IN 4 18 #define CLK_TOP_MAINPLL_806M 5 19 #define CLK_TOP_MAINPLL_537P3M 6 20 #define CLK_TOP_MAINPLL_322P4M 7 21 #define CLK_TOP_MAINPLL_230P3M 8 22 #define CLK_TOP_UNIVPLL_624M 9 23 #define CLK_TOP_UNIVPLL_416M 10 24 #define CLK_TOP_UNIVPLL_249P6M 11 25 #define CLK_TOP_UNIVPLL_178P3M 12 26 #define CLK_TOP_UNIVPLL_48M 13 27 #define CLK_TOP_MMPLL_D2 14 28 #define CLK_TOP_MMPLL_D3 15 29 #define CLK_TOP_MMPLL_D5 16 30 #define CLK_TOP_MMPLL_D7 17 31 #define CLK_TOP_MMPLL_D4 18 32 #define CLK_TOP_MMPLL_D6 19 33 #define CLK_TOP_SYSPLL_D2 20 34 #define CLK_TOP_SYSPLL_D4 21 35 #define CLK_TOP_SYSPLL_D6 22 36 #define CLK_TOP_SYSPLL_D8 23 37 #define CLK_TOP_SYSPLL_D10 24 38 #define CLK_TOP_SYSPLL_D12 25 39 #define CLK_TOP_SYSPLL_D16 26 40 #define CLK_TOP_SYSPLL_D24 27 41 #define CLK_TOP_SYSPLL_D3 28 42 #define CLK_TOP_SYSPLL_D2P5 29 43 #define CLK_TOP_SYSPLL_D5 30 44 #define CLK_TOP_SYSPLL_D3P5 31 45 #define CLK_TOP_UNIVPLL1_D2 32 46 #define CLK_TOP_UNIVPLL1_D4 33 47 #define CLK_TOP_UNIVPLL1_D6 34 48 #define CLK_TOP_UNIVPLL1_D8 35 49 #define CLK_TOP_UNIVPLL1_D10 36 50 #define CLK_TOP_UNIVPLL2_D2 37 51 #define CLK_TOP_UNIVPLL2_D4 38 52 #define CLK_TOP_UNIVPLL2_D6 39 53 #define CLK_TOP_UNIVPLL2_D8 40 54 #define CLK_TOP_UNIVPLL_D3 41 55 #define CLK_TOP_UNIVPLL_D5 42 56 #define CLK_TOP_UNIVPLL_D7 43 57 #define CLK_TOP_UNIVPLL_D10 44 58 #define CLK_TOP_UNIVPLL_D26 45 59 #define CLK_TOP_APLL 46 60 #define CLK_TOP_APLL_D4 47 61 #define CLK_TOP_APLL_D8 48 62 #define CLK_TOP_APLL_D16 49 63 #define CLK_TOP_APLL_D24 50 64 #define CLK_TOP_LVDSPLL_D2 51 65 #define CLK_TOP_LVDSPLL_D4 52 66 #define CLK_TOP_LVDSPLL_D8 53 67 #define CLK_TOP_LVDSTX_CLKDIG_CT 54 68 #define CLK_TOP_VPLL_DPIX 55 69 #define CLK_TOP_TVHDMI_H 56 70 #define CLK_TOP_HDMITX_CLKDIG_D2 57 71 #define CLK_TOP_HDMITX_CLKDIG_D3 58 72 #define CLK_TOP_TVHDMI_D2 59 73 #define CLK_TOP_TVHDMI_D4 60 74 #define CLK_TOP_MEMPLL_MCK_D4 61 75 #define CLK_TOP_AXI_SEL 62 76 #define CLK_TOP_SMI_SEL 63 77 #define CLK_TOP_MFG_SEL 64 78 #define CLK_TOP_IRDA_SEL 65 79 #define CLK_TOP_CAM_SEL 66 80 #define CLK_TOP_AUD_INTBUS_SEL 67 81 #define CLK_TOP_JPG_SEL 68 82 #define CLK_TOP_DISP_SEL 69 83 #define CLK_TOP_MSDC30_1_SEL 70 84 #define CLK_TOP_MSDC30_2_SEL 71 85 #define CLK_TOP_MSDC30_3_SEL 72 86 #define CLK_TOP_MSDC30_4_SEL 73 87 #define CLK_TOP_USB20_SEL 74 88 #define CLK_TOP_VENC_SEL 75 89 #define CLK_TOP_SPI_SEL 76 90 #define CLK_TOP_UART_SEL 77 91 #define CLK_TOP_MEM_SEL 78 92 #define CLK_TOP_CAMTG_SEL 79 93 #define CLK_TOP_AUDIO_SEL 80 94 #define CLK_TOP_FIX_SEL 81 95 #define CLK_TOP_VDEC_SEL 82 96 #define CLK_TOP_DDRPHYCFG_SEL 83 97 #define CLK_TOP_DPILVDS_SEL 84 98 #define CLK_TOP_PMICSPI_SEL 85 99 #define CLK_TOP_MSDC30_0_SEL 86 100 #define CLK_TOP_SMI_MFG_AS_SEL 87 101 #define CLK_TOP_GCPU_SEL 88 102 #define CLK_TOP_DPI1_SEL 89 103 #define CLK_TOP_CCI_SEL 90 104 #define CLK_TOP_APLL_SEL 91 105 #define CLK_TOP_HDMIPLL_SEL 92 106 #define CLK_TOP_NR_CLK 93 107 108 /* APMIXED_SYS */ 109 110 #define CLK_APMIXED_ARMPLL1 1 111 #define CLK_APMIXED_ARMPLL2 2 112 #define CLK_APMIXED_MAINPLL 3 113 #define CLK_APMIXED_UNIVPLL 4 114 #define CLK_APMIXED_MMPLL 5 115 #define CLK_APMIXED_MSDCPLL 6 116 #define CLK_APMIXED_TVDPLL 7 117 #define CLK_APMIXED_LVDSPLL 8 118 #define CLK_APMIXED_AUDPLL 9 119 #define CLK_APMIXED_VDECPLL 10 120 #define CLK_APMIXED_NR_CLK 11 121 122 /* INFRA_SYS */ 123 124 #define CLK_INFRA_PMIC_WRAP 1 125 #define CLK_INFRA_PMICSPI 2 126 #define CLK_INFRA_CCIF1_AP_CTRL 3 127 #define CLK_INFRA_CCIF0_AP_CTRL 4 128 #define CLK_INFRA_KP 5 129 #define CLK_INFRA_CPUM 6 130 #define CLK_INFRA_M4U 7 131 #define CLK_INFRA_MFGAXI 8 132 #define CLK_INFRA_DEVAPC 9 133 #define CLK_INFRA_AUDIO 10 134 #define CLK_INFRA_MFG_BUS 11 135 #define CLK_INFRA_SMI 12 136 #define CLK_INFRA_DBGCLK 13 137 #define CLK_INFRA_NR_CLK 14 138 139 /* PERI_SYS */ 140 141 #define CLK_PERI_I2C5 1 142 #define CLK_PERI_I2C4 2 143 #define CLK_PERI_I2C3 3 144 #define CLK_PERI_I2C2 4 145 #define CLK_PERI_I2C1 5 146 #define CLK_PERI_I2C0 6 147 #define CLK_PERI_UART3 7 148 #define CLK_PERI_UART2 8 149 #define CLK_PERI_UART1 9 150 #define CLK_PERI_UART0 10 151 #define CLK_PERI_IRDA 11 152 #define CLK_PERI_NLI 12 153 #define CLK_PERI_MD_HIF 13 154 #define CLK_PERI_AP_HIF 14 155 #define CLK_PERI_MSDC30_3 15 156 #define CLK_PERI_MSDC30_2 16 157 #define CLK_PERI_MSDC30_1 17 158 #define CLK_PERI_MSDC20_2 18 159 #define CLK_PERI_MSDC20_1 19 160 #define CLK_PERI_AP_DMA 20 161 #define CLK_PERI_USB1 21 162 #define CLK_PERI_USB0 22 163 #define CLK_PERI_PWM 23 164 #define CLK_PERI_PWM7 24 165 #define CLK_PERI_PWM6 25 166 #define CLK_PERI_PWM5 26 167 #define CLK_PERI_PWM4 27 168 #define CLK_PERI_PWM3 28 169 #define CLK_PERI_PWM2 29 170 #define CLK_PERI_PWM1 30 171 #define CLK_PERI_THERM 31 172 #define CLK_PERI_NFI 32 173 #define CLK_PERI_USBSLV 33 174 #define CLK_PERI_USB1_MCU 34 175 #define CLK_PERI_USB0_MCU 35 176 #define CLK_PERI_GCPU 36 177 #define CLK_PERI_FHCTL 37 178 #define CLK_PERI_SPI1 38 179 #define CLK_PERI_AUXADC 39 180 #define CLK_PERI_PERI_PWRAP 40 181 #define CLK_PERI_I2C6 41 182 #define CLK_PERI_UART0_SEL 42 183 #define CLK_PERI_UART1_SEL 43 184 #define CLK_PERI_UART2_SEL 44 185 #define CLK_PERI_UART3_SEL 45 186 #define CLK_PERI_NR_CLK 46 187 188 #endif /* _DT_BINDINGS_CLK_MT8135_H */ 189
Indexes created Fri Oct 03 17:10:05 GMT 2025