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      1 /*	$NetBSD: sun50i-a100-ccu.h,v 1.1.1.1 2021/11/07 16:49:59 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
      4 /*
      5  * Copyright (c) 2020 Yangtao Li <frank (at) allwinnertech.com>
      6  */
      7 
      8 #ifndef _DT_BINDINGS_CLK_SUN50I_A100_H_
      9 #define _DT_BINDINGS_CLK_SUN50I_A100_H_
     10 
     11 #define CLK_PLL_PERIPH0		3
     12 
     13 #define CLK_CPUX		24
     14 
     15 #define CLK_APB1		29
     16 
     17 #define CLK_MBUS		31
     18 #define CLK_DE			32
     19 #define CLK_BUS_DE		33
     20 #define CLK_G2D			34
     21 #define CLK_BUS_G2D		35
     22 #define CLK_GPU			36
     23 #define CLK_BUS_GPU		37
     24 #define CLK_CE			38
     25 #define CLK_BUS_CE		39
     26 #define CLK_VE			40
     27 #define CLK_BUS_VE		41
     28 #define CLK_BUS_DMA		42
     29 #define CLK_BUS_MSGBOX		43
     30 #define CLK_BUS_SPINLOCK	44
     31 #define CLK_BUS_HSTIMER		45
     32 #define CLK_AVS			46
     33 #define CLK_BUS_DBG		47
     34 #define CLK_BUS_PSI		48
     35 #define CLK_BUS_PWM		49
     36 #define CLK_BUS_IOMMU		50
     37 #define CLK_MBUS_DMA		51
     38 #define CLK_MBUS_VE		52
     39 #define CLK_MBUS_CE		53
     40 #define CLK_MBUS_NAND		54
     41 #define CLK_MBUS_CSI		55
     42 #define CLK_MBUS_ISP		56
     43 #define CLK_MBUS_G2D		57
     44 
     45 #define CLK_NAND0		59
     46 #define CLK_NAND1		60
     47 #define CLK_BUS_NAND		61
     48 #define CLK_MMC0		62
     49 #define CLK_MMC1		63
     50 #define CLK_MMC2		64
     51 #define CLK_MMC3		65
     52 #define CLK_BUS_MMC0		66
     53 #define CLK_BUS_MMC1		67
     54 #define CLK_BUS_MMC2		68
     55 #define CLK_BUS_UART0		69
     56 #define CLK_BUS_UART1		70
     57 #define CLK_BUS_UART2		71
     58 #define CLK_BUS_UART3		72
     59 #define CLK_BUS_UART4		73
     60 #define CLK_BUS_I2C0		74
     61 #define CLK_BUS_I2C1		75
     62 #define CLK_BUS_I2C2		76
     63 #define CLK_BUS_I2C3		77
     64 #define CLK_SPI0		78
     65 #define CLK_SPI1		79
     66 #define CLK_SPI2		80
     67 #define CLK_BUS_SPI0		81
     68 #define CLK_BUS_SPI1		82
     69 #define CLK_BUS_SPI2		83
     70 #define CLK_EMAC_25M		84
     71 #define CLK_BUS_EMAC		85
     72 #define CLK_IR_RX		86
     73 #define CLK_BUS_IR_RX		87
     74 #define CLK_IR_TX		88
     75 #define CLK_BUS_IR_TX		89
     76 #define CLK_BUS_GPADC		90
     77 #define CLK_BUS_THS		91
     78 #define CLK_I2S0		92
     79 #define CLK_I2S1		93
     80 #define CLK_I2S2		94
     81 #define CLK_I2S3		95
     82 #define CLK_BUS_I2S0		96
     83 #define CLK_BUS_I2S1		97
     84 #define CLK_BUS_I2S2		98
     85 #define CLK_BUS_I2S3		99
     86 #define CLK_SPDIF		100
     87 #define CLK_BUS_SPDIF		101
     88 #define CLK_DMIC		102
     89 #define CLK_BUS_DMIC		103
     90 #define CLK_AUDIO_DAC		104
     91 #define CLK_AUDIO_ADC		105
     92 #define CLK_AUDIO_4X		106
     93 #define CLK_BUS_AUDIO_CODEC	107
     94 #define CLK_USB_OHCI0		108
     95 #define CLK_USB_PHY0		109
     96 #define CLK_USB_OHCI1		110
     97 #define CLK_USB_PHY1		111
     98 #define CLK_BUS_OHCI0		112
     99 #define CLK_BUS_OHCI1		113
    100 #define CLK_BUS_EHCI0		114
    101 #define CLK_BUS_EHCI1		115
    102 #define CLK_BUS_OTG		116
    103 #define CLK_BUS_LRADC		117
    104 #define CLK_BUS_DPSS_TOP0	118
    105 #define CLK_BUS_DPSS_TOP1	119
    106 #define CLK_MIPI_DSI		120
    107 #define CLK_BUS_MIPI_DSI	121
    108 #define CLK_TCON_LCD		122
    109 #define CLK_BUS_TCON_LCD	123
    110 #define CLK_LEDC		124
    111 #define CLK_BUS_LEDC		125
    112 #define CLK_CSI_TOP		126
    113 #define CLK_CSI0_MCLK		127
    114 #define CLK_CSI1_MCLK		128
    115 #define CLK_BUS_CSI		129
    116 #define CLK_CSI_ISP		130
    117 
    118 #endif /* _DT_BINDINGS_CLK_SUN50I_A100_H_ */
    119