1 /* $NetBSD: mt6797-clk.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2017 MediaTek Inc. 6 * Author: Kevin Chen <kevin-cw.chen (at) mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_MT6797_H 10 #define _DT_BINDINGS_CLK_MT6797_H 11 12 /* TOPCKGEN */ 13 #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE 1 14 #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX 2 15 #define CLK_TOP_MUX_AXI 3 16 #define CLK_TOP_MUX_MEM 4 17 #define CLK_TOP_MUX_DDRPHYCFG 5 18 #define CLK_TOP_MUX_MM 6 19 #define CLK_TOP_MUX_PWM 7 20 #define CLK_TOP_MUX_VDEC 8 21 #define CLK_TOP_MUX_VENC 9 22 #define CLK_TOP_MUX_MFG 10 23 #define CLK_TOP_MUX_CAMTG 11 24 #define CLK_TOP_MUX_UART 12 25 #define CLK_TOP_MUX_SPI 13 26 #define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX 14 27 #define CLK_TOP_MUX_USB20 15 28 #define CLK_TOP_MUX_MSDC50_0_HCLK 16 29 #define CLK_TOP_MUX_MSDC50_0 17 30 #define CLK_TOP_MUX_MSDC30_1 18 31 #define CLK_TOP_MUX_MSDC30_2 19 32 #define CLK_TOP_MUX_AUDIO 20 33 #define CLK_TOP_MUX_AUD_INTBUS 21 34 #define CLK_TOP_MUX_PMICSPI 22 35 #define CLK_TOP_MUX_SCP 23 36 #define CLK_TOP_MUX_ATB 24 37 #define CLK_TOP_MUX_MJC 25 38 #define CLK_TOP_MUX_DPI0 26 39 #define CLK_TOP_MUX_AUD_1 27 40 #define CLK_TOP_MUX_AUD_2 28 41 #define CLK_TOP_MUX_SSUSB_TOP_SYS 29 42 #define CLK_TOP_MUX_SPM 30 43 #define CLK_TOP_MUX_BSI_SPI 31 44 #define CLK_TOP_MUX_AUDIO_H 32 45 #define CLK_TOP_MUX_ANC_MD32 33 46 #define CLK_TOP_MUX_MFG_52M 34 47 #define CLK_TOP_SYSPLL_CK 35 48 #define CLK_TOP_SYSPLL_D2 36 49 #define CLK_TOP_SYSPLL1_D2 37 50 #define CLK_TOP_SYSPLL1_D4 38 51 #define CLK_TOP_SYSPLL1_D8 39 52 #define CLK_TOP_SYSPLL1_D16 40 53 #define CLK_TOP_SYSPLL_D3 41 54 #define CLK_TOP_SYSPLL_D3_D3 42 55 #define CLK_TOP_SYSPLL2_D2 43 56 #define CLK_TOP_SYSPLL2_D4 44 57 #define CLK_TOP_SYSPLL2_D8 45 58 #define CLK_TOP_SYSPLL_D5 46 59 #define CLK_TOP_SYSPLL3_D2 47 60 #define CLK_TOP_SYSPLL3_D4 48 61 #define CLK_TOP_SYSPLL_D7 49 62 #define CLK_TOP_SYSPLL4_D2 50 63 #define CLK_TOP_SYSPLL4_D4 51 64 #define CLK_TOP_UNIVPLL_CK 52 65 #define CLK_TOP_UNIVPLL_D7 53 66 #define CLK_TOP_UNIVPLL_D26 54 67 #define CLK_TOP_SSUSB_PHY_48M_CK 55 68 #define CLK_TOP_USB_PHY48M_CK 56 69 #define CLK_TOP_UNIVPLL_D2 57 70 #define CLK_TOP_UNIVPLL1_D2 58 71 #define CLK_TOP_UNIVPLL1_D4 59 72 #define CLK_TOP_UNIVPLL1_D8 60 73 #define CLK_TOP_UNIVPLL_D3 61 74 #define CLK_TOP_UNIVPLL2_D2 62 75 #define CLK_TOP_UNIVPLL2_D4 63 76 #define CLK_TOP_UNIVPLL2_D8 64 77 #define CLK_TOP_UNIVPLL_D5 65 78 #define CLK_TOP_UNIVPLL3_D2 66 79 #define CLK_TOP_UNIVPLL3_D4 67 80 #define CLK_TOP_UNIVPLL3_D8 68 81 #define CLK_TOP_ULPOSC_CK_ORG 69 82 #define CLK_TOP_ULPOSC_CK 70 83 #define CLK_TOP_ULPOSC_D2 71 84 #define CLK_TOP_ULPOSC_D3 72 85 #define CLK_TOP_ULPOSC_D4 73 86 #define CLK_TOP_ULPOSC_D8 74 87 #define CLK_TOP_ULPOSC_D10 75 88 #define CLK_TOP_APLL1_CK 76 89 #define CLK_TOP_APLL2_CK 77 90 #define CLK_TOP_MFGPLL_CK 78 91 #define CLK_TOP_MFGPLL_D2 79 92 #define CLK_TOP_IMGPLL_CK 80 93 #define CLK_TOP_IMGPLL_D2 81 94 #define CLK_TOP_IMGPLL_D4 82 95 #define CLK_TOP_CODECPLL_CK 83 96 #define CLK_TOP_CODECPLL_D2 84 97 #define CLK_TOP_VDECPLL_CK 85 98 #define CLK_TOP_TVDPLL_CK 86 99 #define CLK_TOP_TVDPLL_D2 87 100 #define CLK_TOP_TVDPLL_D4 88 101 #define CLK_TOP_TVDPLL_D8 89 102 #define CLK_TOP_TVDPLL_D16 90 103 #define CLK_TOP_MSDCPLL_CK 91 104 #define CLK_TOP_MSDCPLL_D2 92 105 #define CLK_TOP_MSDCPLL_D4 93 106 #define CLK_TOP_MSDCPLL_D8 94 107 #define CLK_TOP_NR 95 108 109 /* APMIXED_SYS */ 110 #define CLK_APMIXED_MAINPLL 1 111 #define CLK_APMIXED_UNIVPLL 2 112 #define CLK_APMIXED_MFGPLL 3 113 #define CLK_APMIXED_MSDCPLL 4 114 #define CLK_APMIXED_IMGPLL 5 115 #define CLK_APMIXED_TVDPLL 6 116 #define CLK_APMIXED_CODECPLL 7 117 #define CLK_APMIXED_VDECPLL 8 118 #define CLK_APMIXED_APLL1 9 119 #define CLK_APMIXED_APLL2 10 120 #define CLK_APMIXED_NR 11 121 122 /* INFRA_SYS */ 123 #define CLK_INFRA_PMIC_TMR 1 124 #define CLK_INFRA_PMIC_AP 2 125 #define CLK_INFRA_PMIC_MD 3 126 #define CLK_INFRA_PMIC_CONN 4 127 #define CLK_INFRA_SCP 5 128 #define CLK_INFRA_SEJ 6 129 #define CLK_INFRA_APXGPT 7 130 #define CLK_INFRA_SEJ_13M 8 131 #define CLK_INFRA_ICUSB 9 132 #define CLK_INFRA_GCE 10 133 #define CLK_INFRA_THERM 11 134 #define CLK_INFRA_I2C0 12 135 #define CLK_INFRA_I2C1 13 136 #define CLK_INFRA_I2C2 14 137 #define CLK_INFRA_I2C3 15 138 #define CLK_INFRA_PWM_HCLK 16 139 #define CLK_INFRA_PWM1 17 140 #define CLK_INFRA_PWM2 18 141 #define CLK_INFRA_PWM3 19 142 #define CLK_INFRA_PWM4 20 143 #define CLK_INFRA_PWM 21 144 #define CLK_INFRA_UART0 22 145 #define CLK_INFRA_UART1 23 146 #define CLK_INFRA_UART2 24 147 #define CLK_INFRA_UART3 25 148 #define CLK_INFRA_MD2MD_CCIF_0 26 149 #define CLK_INFRA_MD2MD_CCIF_1 27 150 #define CLK_INFRA_MD2MD_CCIF_2 28 151 #define CLK_INFRA_FHCTL 29 152 #define CLK_INFRA_BTIF 30 153 #define CLK_INFRA_MD2MD_CCIF_3 31 154 #define CLK_INFRA_SPI 32 155 #define CLK_INFRA_MSDC0 33 156 #define CLK_INFRA_MD2MD_CCIF_4 34 157 #define CLK_INFRA_MSDC1 35 158 #define CLK_INFRA_MSDC2 36 159 #define CLK_INFRA_MD2MD_CCIF_5 37 160 #define CLK_INFRA_GCPU 38 161 #define CLK_INFRA_TRNG 39 162 #define CLK_INFRA_AUXADC 40 163 #define CLK_INFRA_CPUM 41 164 #define CLK_INFRA_AP_C2K_CCIF_0 42 165 #define CLK_INFRA_AP_C2K_CCIF_1 43 166 #define CLK_INFRA_CLDMA 44 167 #define CLK_INFRA_DISP_PWM 45 168 #define CLK_INFRA_AP_DMA 46 169 #define CLK_INFRA_DEVICE_APC 47 170 #define CLK_INFRA_L2C_SRAM 48 171 #define CLK_INFRA_CCIF_AP 49 172 #define CLK_INFRA_AUDIO 50 173 #define CLK_INFRA_CCIF_MD 51 174 #define CLK_INFRA_DRAMC_F26M 52 175 #define CLK_INFRA_I2C4 53 176 #define CLK_INFRA_I2C_APPM 54 177 #define CLK_INFRA_I2C_GPUPM 55 178 #define CLK_INFRA_I2C2_IMM 56 179 #define CLK_INFRA_I2C2_ARB 57 180 #define CLK_INFRA_I2C3_IMM 58 181 #define CLK_INFRA_I2C3_ARB 59 182 #define CLK_INFRA_I2C5 60 183 #define CLK_INFRA_SYS_CIRQ 61 184 #define CLK_INFRA_SPI1 62 185 #define CLK_INFRA_DRAMC_B_F26M 63 186 #define CLK_INFRA_ANC_MD32 64 187 #define CLK_INFRA_ANC_MD32_32K 65 188 #define CLK_INFRA_DVFS_SPM1 66 189 #define CLK_INFRA_AES_TOP0 67 190 #define CLK_INFRA_AES_TOP1 68 191 #define CLK_INFRA_SSUSB_BUS 69 192 #define CLK_INFRA_SPI2 70 193 #define CLK_INFRA_SPI3 71 194 #define CLK_INFRA_SPI4 72 195 #define CLK_INFRA_SPI5 73 196 #define CLK_INFRA_IRTX 74 197 #define CLK_INFRA_SSUSB_SYS 75 198 #define CLK_INFRA_SSUSB_REF 76 199 #define CLK_INFRA_AUDIO_26M 77 200 #define CLK_INFRA_AUDIO_26M_PAD_TOP 78 201 #define CLK_INFRA_MODEM_TEMP_SHARE 79 202 #define CLK_INFRA_VAD_WRAP_SOC 80 203 #define CLK_INFRA_DRAMC_CONF 81 204 #define CLK_INFRA_DRAMC_B_CONF 82 205 #define CLK_INFRA_MFG_VCG 83 206 #define CLK_INFRA_13M 84 207 #define CLK_INFRA_NR 85 208 209 /* IMG_SYS */ 210 #define CLK_IMG_FDVT 1 211 #define CLK_IMG_DPE 2 212 #define CLK_IMG_DIP 3 213 #define CLK_IMG_LARB6 4 214 #define CLK_IMG_NR 5 215 216 /* MM_SYS */ 217 #define CLK_MM_SMI_COMMON 1 218 #define CLK_MM_SMI_LARB0 2 219 #define CLK_MM_SMI_LARB5 3 220 #define CLK_MM_CAM_MDP 4 221 #define CLK_MM_MDP_RDMA0 5 222 #define CLK_MM_MDP_RDMA1 6 223 #define CLK_MM_MDP_RSZ0 7 224 #define CLK_MM_MDP_RSZ1 8 225 #define CLK_MM_MDP_RSZ2 9 226 #define CLK_MM_MDP_TDSHP 10 227 #define CLK_MM_MDP_COLOR 11 228 #define CLK_MM_MDP_WDMA 12 229 #define CLK_MM_MDP_WROT0 13 230 #define CLK_MM_MDP_WROT1 14 231 #define CLK_MM_FAKE_ENG 15 232 #define CLK_MM_DISP_OVL0 16 233 #define CLK_MM_DISP_OVL1 17 234 #define CLK_MM_DISP_OVL0_2L 18 235 #define CLK_MM_DISP_OVL1_2L 19 236 #define CLK_MM_DISP_RDMA0 20 237 #define CLK_MM_DISP_RDMA1 21 238 #define CLK_MM_DISP_WDMA0 22 239 #define CLK_MM_DISP_WDMA1 23 240 #define CLK_MM_DISP_COLOR 24 241 #define CLK_MM_DISP_CCORR 25 242 #define CLK_MM_DISP_AAL 26 243 #define CLK_MM_DISP_GAMMA 27 244 #define CLK_MM_DISP_OD 28 245 #define CLK_MM_DISP_DITHER 29 246 #define CLK_MM_DISP_UFOE 30 247 #define CLK_MM_DISP_DSC 31 248 #define CLK_MM_DISP_SPLIT 32 249 #define CLK_MM_DSI0_MM_CLOCK 33 250 #define CLK_MM_DSI1_MM_CLOCK 34 251 #define CLK_MM_DPI_MM_CLOCK 35 252 #define CLK_MM_DPI_INTERFACE_CLOCK 36 253 #define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK 37 254 #define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK 38 255 #define CLK_MM_DISP_OVL0_MOUT_CLOCK 39 256 #define CLK_MM_FAKE_ENG2 40 257 #define CLK_MM_DSI0_INTERFACE_CLOCK 41 258 #define CLK_MM_DSI1_INTERFACE_CLOCK 42 259 #define CLK_MM_NR 43 260 261 /* VDEC_SYS */ 262 #define CLK_VDEC_CKEN_ENG 1 263 #define CLK_VDEC_ACTIVE 2 264 #define CLK_VDEC_CKEN 3 265 #define CLK_VDEC_LARB1_CKEN 4 266 #define CLK_VDEC_NR 5 267 268 /* VENC_SYS */ 269 #define CLK_VENC_0 1 270 #define CLK_VENC_1 2 271 #define CLK_VENC_2 3 272 #define CLK_VENC_3 4 273 #define CLK_VENC_NR 5 274 275 #endif /* _DT_BINDINGS_CLK_MT6797_H */ 276
Indexes created Tue Sep 30 20:09:53 GMT 2025