1 /* $NetBSD: mt2701-clk.h,v 1.1.1.5 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2014 MediaTek Inc. 6 * Author: Shunli Wang <shunli.wang (at) mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_MT2701_H 10 #define _DT_BINDINGS_CLK_MT2701_H 11 12 /* TOPCKGEN */ 13 #define CLK_TOP_SYSPLL 1 14 #define CLK_TOP_SYSPLL_D2 2 15 #define CLK_TOP_SYSPLL_D3 3 16 #define CLK_TOP_SYSPLL_D5 4 17 #define CLK_TOP_SYSPLL_D7 5 18 #define CLK_TOP_SYSPLL1_D2 6 19 #define CLK_TOP_SYSPLL1_D4 7 20 #define CLK_TOP_SYSPLL1_D8 8 21 #define CLK_TOP_SYSPLL1_D16 9 22 #define CLK_TOP_SYSPLL2_D2 10 23 #define CLK_TOP_SYSPLL2_D4 11 24 #define CLK_TOP_SYSPLL2_D8 12 25 #define CLK_TOP_SYSPLL3_D2 13 26 #define CLK_TOP_SYSPLL3_D4 14 27 #define CLK_TOP_SYSPLL4_D2 15 28 #define CLK_TOP_SYSPLL4_D4 16 29 #define CLK_TOP_UNIVPLL 17 30 #define CLK_TOP_UNIVPLL_D2 18 31 #define CLK_TOP_UNIVPLL_D3 19 32 #define CLK_TOP_UNIVPLL_D5 20 33 #define CLK_TOP_UNIVPLL_D7 21 34 #define CLK_TOP_UNIVPLL_D26 22 35 #define CLK_TOP_UNIVPLL_D52 23 36 #define CLK_TOP_UNIVPLL_D108 24 37 #define CLK_TOP_USB_PHY48M 25 38 #define CLK_TOP_UNIVPLL1_D2 26 39 #define CLK_TOP_UNIVPLL1_D4 27 40 #define CLK_TOP_UNIVPLL1_D8 28 41 #define CLK_TOP_UNIVPLL2_D2 29 42 #define CLK_TOP_UNIVPLL2_D4 30 43 #define CLK_TOP_UNIVPLL2_D8 31 44 #define CLK_TOP_UNIVPLL2_D16 32 45 #define CLK_TOP_UNIVPLL2_D32 33 46 #define CLK_TOP_UNIVPLL3_D2 34 47 #define CLK_TOP_UNIVPLL3_D4 35 48 #define CLK_TOP_UNIVPLL3_D8 36 49 #define CLK_TOP_MSDCPLL 37 50 #define CLK_TOP_MSDCPLL_D2 38 51 #define CLK_TOP_MSDCPLL_D4 39 52 #define CLK_TOP_MSDCPLL_D8 40 53 #define CLK_TOP_MMPLL 41 54 #define CLK_TOP_MMPLL_D2 42 55 #define CLK_TOP_DMPLL 43 56 #define CLK_TOP_DMPLL_D2 44 57 #define CLK_TOP_DMPLL_D4 45 58 #define CLK_TOP_DMPLL_X2 46 59 #define CLK_TOP_TVDPLL 47 60 #define CLK_TOP_TVDPLL_D2 48 61 #define CLK_TOP_TVDPLL_D4 49 62 #define CLK_TOP_TVD2PLL 50 63 #define CLK_TOP_TVD2PLL_D2 51 64 #define CLK_TOP_HADDS2PLL_98M 52 65 #define CLK_TOP_HADDS2PLL_294M 53 66 #define CLK_TOP_HADDS2_FB 54 67 #define CLK_TOP_MIPIPLL_D2 55 68 #define CLK_TOP_MIPIPLL_D4 56 69 #define CLK_TOP_HDMIPLL 57 70 #define CLK_TOP_HDMIPLL_D2 58 71 #define CLK_TOP_HDMIPLL_D3 59 72 #define CLK_TOP_HDMI_SCL_RX 60 73 #define CLK_TOP_HDMI_0_PIX340M 61 74 #define CLK_TOP_HDMI_0_DEEP340M 62 75 #define CLK_TOP_HDMI_0_PLL340M 63 76 #define CLK_TOP_AUD1PLL_98M 64 77 #define CLK_TOP_AUD2PLL_90M 65 78 #define CLK_TOP_AUDPLL 66 79 #define CLK_TOP_AUDPLL_D4 67 80 #define CLK_TOP_AUDPLL_D8 68 81 #define CLK_TOP_AUDPLL_D16 69 82 #define CLK_TOP_AUDPLL_D24 70 83 #define CLK_TOP_ETHPLL_500M 71 84 #define CLK_TOP_VDECPLL 72 85 #define CLK_TOP_VENCPLL 73 86 #define CLK_TOP_MIPIPLL 74 87 #define CLK_TOP_ARMPLL_1P3G 75 88 89 #define CLK_TOP_MM_SEL 76 90 #define CLK_TOP_DDRPHYCFG_SEL 77 91 #define CLK_TOP_MEM_SEL 78 92 #define CLK_TOP_AXI_SEL 79 93 #define CLK_TOP_CAMTG_SEL 80 94 #define CLK_TOP_MFG_SEL 81 95 #define CLK_TOP_VDEC_SEL 82 96 #define CLK_TOP_PWM_SEL 83 97 #define CLK_TOP_MSDC30_0_SEL 84 98 #define CLK_TOP_USB20_SEL 85 99 #define CLK_TOP_SPI0_SEL 86 100 #define CLK_TOP_UART_SEL 87 101 #define CLK_TOP_AUDINTBUS_SEL 88 102 #define CLK_TOP_AUDIO_SEL 89 103 #define CLK_TOP_MSDC30_2_SEL 90 104 #define CLK_TOP_MSDC30_1_SEL 91 105 #define CLK_TOP_DPI1_SEL 92 106 #define CLK_TOP_DPI0_SEL 93 107 #define CLK_TOP_SCP_SEL 94 108 #define CLK_TOP_PMICSPI_SEL 95 109 #define CLK_TOP_APLL_SEL 96 110 #define CLK_TOP_HDMI_SEL 97 111 #define CLK_TOP_TVE_SEL 98 112 #define CLK_TOP_EMMC_HCLK_SEL 99 113 #define CLK_TOP_NFI2X_SEL 100 114 #define CLK_TOP_RTC_SEL 101 115 #define CLK_TOP_OSD_SEL 102 116 #define CLK_TOP_NR_SEL 103 117 #define CLK_TOP_DI_SEL 104 118 #define CLK_TOP_FLASH_SEL 105 119 #define CLK_TOP_ASM_M_SEL 106 120 #define CLK_TOP_ASM_I_SEL 107 121 #define CLK_TOP_INTDIR_SEL 108 122 #define CLK_TOP_HDMIRX_BIST_SEL 109 123 #define CLK_TOP_ETHIF_SEL 110 124 #define CLK_TOP_MS_CARD_SEL 111 125 #define CLK_TOP_ASM_H_SEL 112 126 #define CLK_TOP_SPI1_SEL 113 127 #define CLK_TOP_CMSYS_SEL 114 128 #define CLK_TOP_MSDC30_3_SEL 115 129 #define CLK_TOP_HDMIRX26_24_SEL 116 130 #define CLK_TOP_AUD2DVD_SEL 117 131 #define CLK_TOP_8BDAC_SEL 118 132 #define CLK_TOP_SPI2_SEL 119 133 #define CLK_TOP_AUD_MUX1_SEL 120 134 #define CLK_TOP_AUD_MUX2_SEL 121 135 #define CLK_TOP_AUDPLL_MUX_SEL 122 136 #define CLK_TOP_AUD_K1_SRC_SEL 123 137 #define CLK_TOP_AUD_K2_SRC_SEL 124 138 #define CLK_TOP_AUD_K3_SRC_SEL 125 139 #define CLK_TOP_AUD_K4_SRC_SEL 126 140 #define CLK_TOP_AUD_K5_SRC_SEL 127 141 #define CLK_TOP_AUD_K6_SRC_SEL 128 142 #define CLK_TOP_PADMCLK_SEL 129 143 #define CLK_TOP_AUD_EXTCK1_DIV 130 144 #define CLK_TOP_AUD_EXTCK2_DIV 131 145 #define CLK_TOP_AUD_MUX1_DIV 132 146 #define CLK_TOP_AUD_MUX2_DIV 133 147 #define CLK_TOP_AUD_K1_SRC_DIV 134 148 #define CLK_TOP_AUD_K2_SRC_DIV 135 149 #define CLK_TOP_AUD_K3_SRC_DIV 136 150 #define CLK_TOP_AUD_K4_SRC_DIV 137 151 #define CLK_TOP_AUD_K5_SRC_DIV 138 152 #define CLK_TOP_AUD_K6_SRC_DIV 139 153 #define CLK_TOP_AUD_I2S1_MCLK 140 154 #define CLK_TOP_AUD_I2S2_MCLK 141 155 #define CLK_TOP_AUD_I2S3_MCLK 142 156 #define CLK_TOP_AUD_I2S4_MCLK 143 157 #define CLK_TOP_AUD_I2S5_MCLK 144 158 #define CLK_TOP_AUD_I2S6_MCLK 145 159 #define CLK_TOP_AUD_48K_TIMING 146 160 #define CLK_TOP_AUD_44K_TIMING 147 161 162 #define CLK_TOP_32K_INTERNAL 148 163 #define CLK_TOP_32K_EXTERNAL 149 164 #define CLK_TOP_CLK26M_D8 150 165 #define CLK_TOP_8BDAC 151 166 #define CLK_TOP_WBG_DIG_416M 152 167 #define CLK_TOP_DPI 153 168 #define CLK_TOP_DSI0_LNTC_DSI 154 169 #define CLK_TOP_AUD_EXT1 155 170 #define CLK_TOP_AUD_EXT2 156 171 #define CLK_TOP_NFI1X_PAD 157 172 #define CLK_TOP_AXISEL_D4 158 173 #define CLK_TOP_NR 159 174 175 /* APMIXEDSYS */ 176 177 #define CLK_APMIXED_ARMPLL 1 178 #define CLK_APMIXED_MAINPLL 2 179 #define CLK_APMIXED_UNIVPLL 3 180 #define CLK_APMIXED_MMPLL 4 181 #define CLK_APMIXED_MSDCPLL 5 182 #define CLK_APMIXED_TVDPLL 6 183 #define CLK_APMIXED_AUD1PLL 7 184 #define CLK_APMIXED_TRGPLL 8 185 #define CLK_APMIXED_ETHPLL 9 186 #define CLK_APMIXED_VDECPLL 10 187 #define CLK_APMIXED_HADDS2PLL 11 188 #define CLK_APMIXED_AUD2PLL 12 189 #define CLK_APMIXED_TVD2PLL 13 190 #define CLK_APMIXED_HDMI_REF 14 191 #define CLK_APMIXED_NR 15 192 193 /* DDRPHY */ 194 195 #define CLK_DDRPHY_VENCPLL 1 196 #define CLK_DDRPHY_NR 2 197 198 /* INFRACFG */ 199 200 #define CLK_INFRA_DBG 1 201 #define CLK_INFRA_SMI 2 202 #define CLK_INFRA_QAXI_CM4 3 203 #define CLK_INFRA_AUD_SPLIN_B 4 204 #define CLK_INFRA_AUDIO 5 205 #define CLK_INFRA_EFUSE 6 206 #define CLK_INFRA_L2C_SRAM 7 207 #define CLK_INFRA_M4U 8 208 #define CLK_INFRA_CONNMCU 9 209 #define CLK_INFRA_TRNG 10 210 #define CLK_INFRA_RAMBUFIF 11 211 #define CLK_INFRA_CPUM 12 212 #define CLK_INFRA_KP 13 213 #define CLK_INFRA_CEC 14 214 #define CLK_INFRA_IRRX 15 215 #define CLK_INFRA_PMICSPI 16 216 #define CLK_INFRA_PMICWRAP 17 217 #define CLK_INFRA_DDCCI 18 218 #define CLK_INFRA_CLK_13M 19 219 #define CLK_INFRA_CPUSEL 20 220 #define CLK_INFRA_NR 21 221 222 /* PERICFG */ 223 224 #define CLK_PERI_NFI 1 225 #define CLK_PERI_THERM 2 226 #define CLK_PERI_PWM1 3 227 #define CLK_PERI_PWM2 4 228 #define CLK_PERI_PWM3 5 229 #define CLK_PERI_PWM4 6 230 #define CLK_PERI_PWM5 7 231 #define CLK_PERI_PWM6 8 232 #define CLK_PERI_PWM7 9 233 #define CLK_PERI_PWM 10 234 #define CLK_PERI_USB0 11 235 #define CLK_PERI_USB1 12 236 #define CLK_PERI_AP_DMA 13 237 #define CLK_PERI_MSDC30_0 14 238 #define CLK_PERI_MSDC30_1 15 239 #define CLK_PERI_MSDC30_2 16 240 #define CLK_PERI_MSDC30_3 17 241 #define CLK_PERI_MSDC50_3 18 242 #define CLK_PERI_NLI 19 243 #define CLK_PERI_UART0 20 244 #define CLK_PERI_UART1 21 245 #define CLK_PERI_UART2 22 246 #define CLK_PERI_UART3 23 247 #define CLK_PERI_BTIF 24 248 #define CLK_PERI_I2C0 25 249 #define CLK_PERI_I2C1 26 250 #define CLK_PERI_I2C2 27 251 #define CLK_PERI_I2C3 28 252 #define CLK_PERI_AUXADC 29 253 #define CLK_PERI_SPI0 30 254 #define CLK_PERI_ETH 31 255 #define CLK_PERI_USB0_MCU 32 256 257 #define CLK_PERI_USB1_MCU 33 258 #define CLK_PERI_USB_SLV 34 259 #define CLK_PERI_GCPU 35 260 #define CLK_PERI_NFI_ECC 36 261 #define CLK_PERI_NFI_PAD 37 262 #define CLK_PERI_FLASH 38 263 #define CLK_PERI_HOST89_INT 39 264 #define CLK_PERI_HOST89_SPI 40 265 #define CLK_PERI_HOST89_DVD 41 266 #define CLK_PERI_SPI1 42 267 #define CLK_PERI_SPI2 43 268 #define CLK_PERI_FCI 44 269 270 #define CLK_PERI_UART0_SEL 45 271 #define CLK_PERI_UART1_SEL 46 272 #define CLK_PERI_UART2_SEL 47 273 #define CLK_PERI_UART3_SEL 48 274 #define CLK_PERI_NR 49 275 276 /* AUDIO */ 277 278 #define CLK_AUD_AFE 1 279 #define CLK_AUD_LRCK_DETECT 2 280 #define CLK_AUD_I2S 3 281 #define CLK_AUD_APLL_TUNER 4 282 #define CLK_AUD_HDMI 5 283 #define CLK_AUD_SPDF 6 284 #define CLK_AUD_SPDF2 7 285 #define CLK_AUD_APLL 8 286 #define CLK_AUD_TML 9 287 #define CLK_AUD_AHB_IDLE_EXT 10 288 #define CLK_AUD_AHB_IDLE_INT 11 289 290 #define CLK_AUD_I2SIN1 12 291 #define CLK_AUD_I2SIN2 13 292 #define CLK_AUD_I2SIN3 14 293 #define CLK_AUD_I2SIN4 15 294 #define CLK_AUD_I2SIN5 16 295 #define CLK_AUD_I2SIN6 17 296 #define CLK_AUD_I2SO1 18 297 #define CLK_AUD_I2SO2 19 298 #define CLK_AUD_I2SO3 20 299 #define CLK_AUD_I2SO4 21 300 #define CLK_AUD_I2SO5 22 301 #define CLK_AUD_I2SO6 23 302 #define CLK_AUD_ASRCI1 24 303 #define CLK_AUD_ASRCI2 25 304 #define CLK_AUD_ASRCO1 26 305 #define CLK_AUD_ASRCO2 27 306 #define CLK_AUD_ASRC11 28 307 #define CLK_AUD_ASRC12 29 308 #define CLK_AUD_HDMIRX 30 309 #define CLK_AUD_INTDIR 31 310 #define CLK_AUD_A1SYS 32 311 #define CLK_AUD_A2SYS 33 312 #define CLK_AUD_AFE_CONN 34 313 #define CLK_AUD_AFE_PCMIF 35 314 #define CLK_AUD_AFE_MRGIF 36 315 316 #define CLK_AUD_MMIF_UL1 37 317 #define CLK_AUD_MMIF_UL2 38 318 #define CLK_AUD_MMIF_UL3 39 319 #define CLK_AUD_MMIF_UL4 40 320 #define CLK_AUD_MMIF_UL5 41 321 #define CLK_AUD_MMIF_UL6 42 322 #define CLK_AUD_MMIF_DL1 43 323 #define CLK_AUD_MMIF_DL2 44 324 #define CLK_AUD_MMIF_DL3 45 325 #define CLK_AUD_MMIF_DL4 46 326 #define CLK_AUD_MMIF_DL5 47 327 #define CLK_AUD_MMIF_DL6 48 328 #define CLK_AUD_MMIF_DLMCH 49 329 #define CLK_AUD_MMIF_ARB1 50 330 #define CLK_AUD_MMIF_AWB1 51 331 #define CLK_AUD_MMIF_AWB2 52 332 #define CLK_AUD_MMIF_DAI 53 333 334 #define CLK_AUD_DMIC1 54 335 #define CLK_AUD_DMIC2 55 336 #define CLK_AUD_ASRCI3 56 337 #define CLK_AUD_ASRCI4 57 338 #define CLK_AUD_ASRCI5 58 339 #define CLK_AUD_ASRCI6 59 340 #define CLK_AUD_ASRCO3 60 341 #define CLK_AUD_ASRCO4 61 342 #define CLK_AUD_ASRCO5 62 343 #define CLK_AUD_ASRCO6 63 344 #define CLK_AUD_MEM_ASRC1 64 345 #define CLK_AUD_MEM_ASRC2 65 346 #define CLK_AUD_MEM_ASRC3 66 347 #define CLK_AUD_MEM_ASRC4 67 348 #define CLK_AUD_MEM_ASRC5 68 349 #define CLK_AUD_DSD_ENC 69 350 #define CLK_AUD_ASRC_BRG 70 351 #define CLK_AUD_NR 71 352 353 /* MMSYS */ 354 355 #define CLK_MM_SMI_COMMON 1 356 #define CLK_MM_SMI_LARB0 2 357 #define CLK_MM_CMDQ 3 358 #define CLK_MM_MUTEX 4 359 #define CLK_MM_DISP_COLOR 5 360 #define CLK_MM_DISP_BLS 6 361 #define CLK_MM_DISP_WDMA 7 362 #define CLK_MM_DISP_RDMA 8 363 #define CLK_MM_DISP_OVL 9 364 #define CLK_MM_MDP_TDSHP 10 365 #define CLK_MM_MDP_WROT 11 366 #define CLK_MM_MDP_WDMA 12 367 #define CLK_MM_MDP_RSZ1 13 368 #define CLK_MM_MDP_RSZ0 14 369 #define CLK_MM_MDP_RDMA 15 370 #define CLK_MM_MDP_BLS_26M 16 371 #define CLK_MM_CAM_MDP 17 372 #define CLK_MM_FAKE_ENG 18 373 #define CLK_MM_MUTEX_32K 19 374 #define CLK_MM_DISP_RDMA1 20 375 #define CLK_MM_DISP_UFOE 21 376 377 #define CLK_MM_DSI_ENGINE 22 378 #define CLK_MM_DSI_DIG 23 379 #define CLK_MM_DPI_DIGL 24 380 #define CLK_MM_DPI_ENGINE 25 381 #define CLK_MM_DPI1_DIGL 26 382 #define CLK_MM_DPI1_ENGINE 27 383 #define CLK_MM_TVE_OUTPUT 28 384 #define CLK_MM_TVE_INPUT 29 385 #define CLK_MM_HDMI_PIXEL 30 386 #define CLK_MM_HDMI_PLL 31 387 #define CLK_MM_HDMI_AUDIO 32 388 #define CLK_MM_HDMI_SPDIF 33 389 #define CLK_MM_TVE_FMM 34 390 #define CLK_MM_NR 35 391 392 /* IMGSYS */ 393 394 #define CLK_IMG_SMI_COMM 1 395 #define CLK_IMG_RESZ 2 396 #define CLK_IMG_JPGDEC_SMI 3 397 #define CLK_IMG_JPGDEC 4 398 #define CLK_IMG_VENC_LT 5 399 #define CLK_IMG_VENC 6 400 #define CLK_IMG_NR 7 401 402 /* VDEC */ 403 404 #define CLK_VDEC_CKGEN 1 405 #define CLK_VDEC_LARB 2 406 #define CLK_VDEC_NR 3 407 408 /* HIFSYS */ 409 410 #define CLK_HIFSYS_USB0PHY 1 411 #define CLK_HIFSYS_USB1PHY 2 412 #define CLK_HIFSYS_PCIE0 3 413 #define CLK_HIFSYS_PCIE1 4 414 #define CLK_HIFSYS_PCIE2 5 415 #define CLK_HIFSYS_NR 6 416 417 /* ETHSYS */ 418 #define CLK_ETHSYS_HSDMA 1 419 #define CLK_ETHSYS_ESW 2 420 #define CLK_ETHSYS_GP2 3 421 #define CLK_ETHSYS_GP1 4 422 #define CLK_ETHSYS_PCM 5 423 #define CLK_ETHSYS_GDMA 6 424 #define CLK_ETHSYS_I2S 7 425 #define CLK_ETHSYS_CRYPTO 8 426 #define CLK_ETHSYS_NR 9 427 428 /* G3DSYS */ 429 #define CLK_G3DSYS_CORE 1 430 #define CLK_G3DSYS_NR 2 431 432 /* BDP */ 433 434 #define CLK_BDP_BRG_BA 1 435 #define CLK_BDP_BRG_DRAM 2 436 #define CLK_BDP_LARB_DRAM 3 437 #define CLK_BDP_WR_VDI_PXL 4 438 #define CLK_BDP_WR_VDI_DRAM 5 439 #define CLK_BDP_WR_B 6 440 #define CLK_BDP_DGI_IN 7 441 #define CLK_BDP_DGI_OUT 8 442 #define CLK_BDP_FMT_MAST_27 9 443 #define CLK_BDP_FMT_B 10 444 #define CLK_BDP_OSD_B 11 445 #define CLK_BDP_OSD_DRAM 12 446 #define CLK_BDP_OSD_AGENT 13 447 #define CLK_BDP_OSD_PXL 14 448 #define CLK_BDP_RLE_B 15 449 #define CLK_BDP_RLE_AGENT 16 450 #define CLK_BDP_RLE_DRAM 17 451 #define CLK_BDP_F27M 18 452 #define CLK_BDP_F27M_VDOUT 19 453 #define CLK_BDP_F27_74_74 20 454 #define CLK_BDP_F2FS 21 455 #define CLK_BDP_F2FS74_148 22 456 #define CLK_BDP_FB 23 457 #define CLK_BDP_VDO_DRAM 24 458 #define CLK_BDP_VDO_2FS 25 459 #define CLK_BDP_VDO_B 26 460 #define CLK_BDP_WR_DI_PXL 27 461 #define CLK_BDP_WR_DI_DRAM 28 462 #define CLK_BDP_WR_DI_B 29 463 #define CLK_BDP_NR_PXL 30 464 #define CLK_BDP_NR_DRAM 31 465 #define CLK_BDP_NR_B 32 466 467 #define CLK_BDP_RX_F 33 468 #define CLK_BDP_RX_X 34 469 #define CLK_BDP_RXPDT 35 470 #define CLK_BDP_RX_CSCL_N 36 471 #define CLK_BDP_RX_CSCL 37 472 #define CLK_BDP_RX_DDCSCL_N 38 473 #define CLK_BDP_RX_DDCSCL 39 474 #define CLK_BDP_RX_VCO 40 475 #define CLK_BDP_RX_DP 41 476 #define CLK_BDP_RX_P 42 477 #define CLK_BDP_RX_M 43 478 #define CLK_BDP_RX_PLL 44 479 #define CLK_BDP_BRG_RT_B 45 480 #define CLK_BDP_BRG_RT_DRAM 46 481 #define CLK_BDP_LARBRT_DRAM 47 482 #define CLK_BDP_TMDS_SYN 48 483 #define CLK_BDP_HDMI_MON 49 484 #define CLK_BDP_NR 50 485 486 #endif /* _DT_BINDINGS_CLK_MT2701_H */ 487
Indexes created Tue Sep 30 11:09:46 GMT 2025