1 /* $NetBSD: mesongx_wdt.c,v 1.3 2022/09/28 10:23:37 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: mesongx_wdt.c,v 1.3 2022/09/28 10:23:37 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/device.h> 36 #include <sys/wdog.h> 37 38 #include <dev/sysmon/sysmonvar.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #define CBUS_REG(x) ((x) << 2) 43 44 #define WATCHDOG_CNTL CBUS_REG(0) 45 #define CNTL_CLK_DIV_EN __BIT(25) 46 #define CNTL_CLK_EN __BIT(24) 47 #define CNTL_SYS_RESET_N_EN __BIT(21) 48 #define CNTL_WATCHDOG_EN __BIT(18) 49 #define CNTL_CLK_DIV_TCNT __BITS(17,0) 50 #define WATCHDOG_CNTL1 CBUS_REG(1) 51 #define WATCHDOG_TCNT CBUS_REG(2) 52 #define WATCHDOG_RESET CBUS_REG(3) 53 54 #define WATCHDOG_PERIOD_DEFAULT 8 55 #define WATCHDOG_PERIOD_MAX 8 56 57 static const struct device_compatible_entry compat_data[] = { 58 { .compat = "amlogic,meson-gx-wdt" }, 59 { .compat = "amlogic,meson-gxbb-wdt" }, 60 DEVICE_COMPAT_EOL 61 }; 62 63 struct mesongx_wdt_softc { 64 device_t sc_dev; 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; 67 68 struct sysmon_wdog sc_wdog; 69 u_int sc_rate; 70 }; 71 72 #define WDT_READ(sc, reg) \ 73 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 74 #define WDT_WRITE(sc, reg, val) \ 75 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 76 77 static int 78 mesongx_wdt_setmode(struct sysmon_wdog *smw) 79 { 80 struct mesongx_wdt_softc * const sc = smw->smw_cookie; 81 82 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 83 WDT_WRITE(sc, WATCHDOG_CNTL, 0); 84 return 0; 85 } 86 87 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 88 sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT; 89 } else if (smw->smw_period == 0 || 90 smw->smw_period > WATCHDOG_PERIOD_MAX) { 91 return EINVAL; 92 } else { 93 sc->sc_wdog.smw_period = smw->smw_period; 94 } 95 96 const u_int tcnt = sc->sc_rate / 1000; 97 98 WDT_WRITE(sc, WATCHDOG_CNTL, 0); 99 WDT_WRITE(sc, WATCHDOG_RESET, 0); 100 WDT_WRITE(sc, WATCHDOG_TCNT, sc->sc_wdog.smw_period * 1000); 101 WDT_WRITE(sc, WATCHDOG_CNTL, 102 __SHIFTIN(tcnt, CNTL_CLK_DIV_TCNT) | 103 CNTL_CLK_DIV_EN | CNTL_CLK_EN | 104 CNTL_SYS_RESET_N_EN | CNTL_WATCHDOG_EN); 105 106 return 0; 107 } 108 109 static int 110 mesongx_wdt_tickle(struct sysmon_wdog *smw) 111 { 112 struct mesongx_wdt_softc * const sc = smw->smw_cookie; 113 114 WDT_WRITE(sc, WATCHDOG_RESET, 0); 115 116 return 0; 117 } 118 119 static int 120 mesongx_wdt_match(device_t parent, cfdata_t cf, void *aux) 121 { 122 struct fdt_attach_args * const faa = aux; 123 124 return of_compatible_match(faa->faa_phandle, compat_data); 125 } 126 127 static void 128 mesongx_wdt_attach(device_t parent, device_t self, void *aux) 129 { 130 struct mesongx_wdt_softc * const sc = device_private(self); 131 struct fdt_attach_args * const faa = aux; 132 const int phandle = faa->faa_phandle; 133 struct clk *clk; 134 bus_addr_t addr; 135 bus_size_t size; 136 137 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 138 aprint_error(": couldn't get registers\n"); 139 return; 140 } 141 142 sc->sc_dev = self; 143 sc->sc_bst = faa->faa_bst; 144 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 145 aprint_error(": couldn't map registers\n"); 146 return; 147 } 148 149 aprint_naive("\n"); 150 aprint_normal(": EE-watchdog\n"); 151 152 clk = fdtbus_clock_get_index(phandle, 0); 153 if (clk != NULL) 154 sc->sc_rate = clk_get_rate(clk); 155 else { 156 aprint_error_dev(self, "WARNING: couldn't get xtal clock, assuming 24 MHz\n"); 157 sc->sc_rate = 24000000; 158 } 159 160 /* Disable watchdog */ 161 WDT_WRITE(sc, WATCHDOG_CNTL, 0); 162 163 /* Register watchdog */ 164 sc->sc_wdog.smw_name = "EE-watchdog"; 165 sc->sc_wdog.smw_setmode = mesongx_wdt_setmode; 166 sc->sc_wdog.smw_tickle = mesongx_wdt_tickle; 167 sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT; 168 sc->sc_wdog.smw_cookie = sc; 169 sysmon_wdog_register(&sc->sc_wdog); 170 } 171 172 CFATTACH_DECL_NEW(mesongx_wdt, sizeof(struct mesongx_wdt_softc), 173 mesongx_wdt_match, mesongx_wdt_attach, NULL, NULL); 174
Indexes created Mon Oct 13 08:09:50 GMT 2025