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    Searched defs:CORE (Results 1 - 6 of 6) sorted by relevancy

  /src/external/gpl3/binutils/dist/gas/config/
tc-mep.h 92 /* Support for core/vliw mode switching. */
93 #define CORE 0
  /src/external/gpl3/binutils.old/dist/gas/config/
tc-mep.h 92 /* Support for core/vliw mode switching. */
93 #define CORE 0
  /src/external/gpl3/gdb.old/dist/opcodes/
aarch64-tbl.h 2719 #define CORE &aarch64_feature_v8
2794 { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
4087 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
4094 {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
  /src/external/gpl3/binutils/dist/opcodes/
aarch64-tbl.h 3113 #define CORE &aarch64_feature_v8
3252 { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
4795 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_SUBCLASS_OTHER, 0, 0, VERIFIER (ldpsw)},
4802 {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_SUBCLASS_OTHER, 0, 0, VERIFIER (ldpsw)},
  /src/external/gpl3/binutils.old/dist/opcodes/
aarch64-tbl.h 3016 #define CORE &aarch64_feature_v8
3127 { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
4571 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_SUBCLASS_OTHER, 0, 0, VERIFIER (ldpsw)},
4578 {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_SUBCLASS_OTHER, 0, 0, VERIFIER (ldpsw)},
  /src/external/gpl3/gdb/dist/opcodes/
aarch64-tbl.h 2868 #define CORE &aarch64_feature_v8
2956 { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
4277 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_SUBCLASS_OTHER, 0, 0, VERIFIER (ldpsw)},
4284 {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, F_SUBCLASS_OTHER, 0, 0, VERIFIER (ldpsw)},

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