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      1 /*	$NetBSD: xlnx-versal-clk.h,v 1.1.1.1 2021/11/07 16:50:00 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 */
      4 /*
      5  *  Copyright (C) 2019 Xilinx Inc.
      6  *
      7  */
      8 
      9 #ifndef _DT_BINDINGS_CLK_VERSAL_H
     10 #define _DT_BINDINGS_CLK_VERSAL_H
     11 
     12 #define PMC_PLL					1
     13 #define APU_PLL					2
     14 #define RPU_PLL					3
     15 #define CPM_PLL					4
     16 #define NOC_PLL					5
     17 #define PLL_MAX					6
     18 #define PMC_PRESRC				7
     19 #define PMC_POSTCLK				8
     20 #define PMC_PLL_OUT				9
     21 #define PPLL					10
     22 #define NOC_PRESRC				11
     23 #define NOC_POSTCLK				12
     24 #define NOC_PLL_OUT				13
     25 #define NPLL					14
     26 #define APU_PRESRC				15
     27 #define APU_POSTCLK				16
     28 #define APU_PLL_OUT				17
     29 #define APLL					18
     30 #define RPU_PRESRC				19
     31 #define RPU_POSTCLK				20
     32 #define RPU_PLL_OUT				21
     33 #define RPLL					22
     34 #define CPM_PRESRC				23
     35 #define CPM_POSTCLK				24
     36 #define CPM_PLL_OUT				25
     37 #define CPLL					26
     38 #define PPLL_TO_XPD				27
     39 #define NPLL_TO_XPD				28
     40 #define APLL_TO_XPD				29
     41 #define RPLL_TO_XPD				30
     42 #define EFUSE_REF				31
     43 #define SYSMON_REF				32
     44 #define IRO_SUSPEND_REF				33
     45 #define USB_SUSPEND				34
     46 #define SWITCH_TIMEOUT				35
     47 #define RCLK_PMC				36
     48 #define RCLK_LPD				37
     49 #define WDT					38
     50 #define TTC0					39
     51 #define TTC1					40
     52 #define TTC2					41
     53 #define TTC3					42
     54 #define GEM_TSU					43
     55 #define GEM_TSU_LB				44
     56 #define MUXED_IRO_DIV2				45
     57 #define MUXED_IRO_DIV4				46
     58 #define PSM_REF					47
     59 #define GEM0_RX					48
     60 #define GEM0_TX					49
     61 #define GEM1_RX					50
     62 #define GEM1_TX					51
     63 #define CPM_CORE_REF				52
     64 #define CPM_LSBUS_REF				53
     65 #define CPM_DBG_REF				54
     66 #define CPM_AUX0_REF				55
     67 #define CPM_AUX1_REF				56
     68 #define QSPI_REF				57
     69 #define OSPI_REF				58
     70 #define SDIO0_REF				59
     71 #define SDIO1_REF				60
     72 #define PMC_LSBUS_REF				61
     73 #define I2C_REF					62
     74 #define TEST_PATTERN_REF			63
     75 #define DFT_OSC_REF				64
     76 #define PMC_PL0_REF				65
     77 #define PMC_PL1_REF				66
     78 #define PMC_PL2_REF				67
     79 #define PMC_PL3_REF				68
     80 #define CFU_REF					69
     81 #define SPARE_REF				70
     82 #define NPI_REF					71
     83 #define HSM0_REF				72
     84 #define HSM1_REF				73
     85 #define SD_DLL_REF				74
     86 #define FPD_TOP_SWITCH				75
     87 #define FPD_LSBUS				76
     88 #define ACPU					77
     89 #define DBG_TRACE				78
     90 #define DBG_FPD					79
     91 #define LPD_TOP_SWITCH				80
     92 #define ADMA					81
     93 #define LPD_LSBUS				82
     94 #define CPU_R5					83
     95 #define CPU_R5_CORE				84
     96 #define CPU_R5_OCM				85
     97 #define CPU_R5_OCM2				86
     98 #define IOU_SWITCH				87
     99 #define GEM0_REF				88
    100 #define GEM1_REF				89
    101 #define GEM_TSU_REF				90
    102 #define USB0_BUS_REF				91
    103 #define UART0_REF				92
    104 #define UART1_REF				93
    105 #define SPI0_REF				94
    106 #define SPI1_REF				95
    107 #define CAN0_REF				96
    108 #define CAN1_REF				97
    109 #define I2C0_REF				98
    110 #define I2C1_REF				99
    111 #define DBG_LPD					100
    112 #define TIMESTAMP_REF				101
    113 #define DBG_TSTMP				102
    114 #define CPM_TOPSW_REF				103
    115 #define USB3_DUAL_REF				104
    116 #define OUTCLK_MAX				105
    117 #define REF_CLK					106
    118 #define PL_ALT_REF_CLK				107
    119 #define MUXED_IRO				108
    120 #define PL_EXT					109
    121 #define PL_LB					110
    122 #define MIO_50_OR_51				111
    123 #define MIO_24_OR_25				112
    124 
    125 #endif
    126