| /src/sys/arch/epoc32/stand/e32boot/ldd/ |
| cpu.h | 1 /* $NetBSD: cpu.h,v 1.1 2013/04/28 12:11:27 kiyohara Exp $ */
28 class CPU {
34 class ARM7 : public CPU {
40 class ARM7TDMI : public CPU {
46 class SA1100 : public CPU {
|
| /src/external/apache2/llvm/dist/clang/lib/Driver/ToolChains/Arch/ |
| M68k.cpp | 26 /// getM68kTargetCPU - Get the (LLVM) name of the 68000 cpu we are targeting.
29 // The canonical CPU name is captalize. However, we allow
34 std::string CPU = std::string(llvm::sys::getHostCPUName());
35 if (!CPU.empty() && CPU != "generic")
36 return CPU;
|
| SystemZ.cpp | 42 std::string CPU = std::string(llvm::sys::getHostCPUName());
43 if (!CPU.empty() && CPU != "generic")
44 return CPU;
|
| X86.cpp | 26 StringRef CPU = A->getValue();
27 if (CPU != "native")
28 return std::string(CPU);
35 CPU = llvm::sys::getHostCPUName();
36 if (!CPU.empty() && CPU != "generic")
37 return std::string(CPU);
43 StringRef CPU;
45 CPU = llvm::StringSwitch<StringRef>(Arch)
51 if (CPU.empty()) { // 32-bit and 64-bit /arch: flags
[all...] |
| PPC.cpp | 23 /// getPPCTargetCPU - Get the (LLVM) name of the PowerPC cpu we are targeting.
29 std::string CPU = std::string(llvm::sys::getHostCPUName());
30 if (!CPU.empty() && CPU != "generic")
31 return CPU;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonELFObjectWriter.cpp | 27 StringRef CPU;
40 CPU(C) {}
301 llvm::createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU) {
302 return std::make_unique<HexagonELFObjectWriter>(OSABI, CPU);
|
| /src/external/gpl3/gdb/dist/sim/mips/ |
| m16run.c | 31 #define CPU cpu
39 sim_cpu *cpu = STATE_CPU (sd, next_cpu_nr); local
40 address_word cia = CPU_PC_GET (cpu);
67 CPU_PC_SET (CPU, cia);
69 cia = CPU_PC_GET (CPU);
|
| micromipsrun.c | 41 #define CPU cpu
44 micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu,
67 sim_engine_abort (sd, cpu, cia,
85 sim_cpu *cpu = STATE_CPU (sd, next_cpu_nr); local
86 micromips32_instruction_address cia = CPU_PC_GET (cpu);
113 micromips_instruction_decode (sd, cpu, cia,
130 CPU_PC_SET (cpu, cia);
132 cia = CPU_PC_GET (cpu);
|
| dv-tx3904cpu.c | 30 tx3904cpu - tx3904 cpu virtual device
145 sim_cpu *cpu = STATE_CPU (sd, 0); /* NB: fix CPU 0. */ local
146 address_word cia = CPU_PC_GET (cpu);
148 #define CPU cpu
154 HW_TRACE ((me, "reset pc=0x%08lx", (long) CPU_PC_GET (cpu)));
160 HW_TRACE ((me, "nmi pc=0x%08lx", (long) CPU_PC_GET (cpu)));
167 (long) CPU_PC_GET (cpu), (long) SR));
195 #undef CPU
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/mips/ |
| m16run.c | 31 #define CPU cpu
39 sim_cpu *cpu = STATE_CPU (sd, next_cpu_nr); local
40 address_word cia = CPU_PC_GET (cpu);
67 CPU_PC_SET (CPU, cia);
69 cia = CPU_PC_GET (CPU);
|
| micromipsrun.c | 41 #define CPU cpu
44 micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu,
67 sim_engine_abort (sd, cpu, cia,
85 sim_cpu *cpu = STATE_CPU (sd, next_cpu_nr); local
86 micromips32_instruction_address cia = CPU_PC_GET (cpu);
113 micromips_instruction_decode (sd, cpu, cia,
130 CPU_PC_SET (cpu, cia);
132 cia = CPU_PC_GET (cpu);
|
| dv-tx3904cpu.c | 30 tx3904cpu - tx3904 cpu virtual device
145 sim_cpu *cpu = STATE_CPU (sd, 0); /* NB: fix CPU 0. */ local
146 address_word cia = CPU_PC_GET (cpu);
148 #define CPU cpu
154 HW_TRACE ((me, "reset pc=0x%08lx", (long) CPU_PC_GET (cpu)));
160 HW_TRACE ((me, "nmi pc=0x%08lx", (long) CPU_PC_GET (cpu)));
167 (long) CPU_PC_GET (cpu), (long) SR));
195 #undef CPU
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/Basic/Targets/ |
| AVR.h | 174 CPU = Name;
179 std::string CPU;
|
| Hexagon.h | 30 std::string CPU;
100 StringRef CPU,
129 CPU = Name;
139 return CPU.find('t') != std::string::npos;
|
| Lanai.h | 26 // The CPU profiles supported by the Lanai backend
30 } CPU;
52 // Set the default CPU to V11
53 CPU = CK_V11;
|
| M68k.h | 36 } CPU = CK_Unknown;
|
| Mips.cpp | 32 return llvm::StringSwitch<bool>(CPU)
189 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
190 if (CPU == "octeon+")
193 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
195 if (StringRef(CPU).startswith("octeon"))
238 Diags.Report(diag::err_target_unsupported_cpu_for_micromips) << CPU;
241 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
244 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
248 // 64-bit ABI's require 64-bit CPU's.
250 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
[all...] |
| SystemZ.h | 28 std::string CPU;
36 : TargetInfo(Triple), CPU("z10"), ISARevision(8),
93 CPU = Name;
94 ISARevision = getISARevision(CPU);
100 StringRef CPU,
102 int ISARevision = getISARevision(CPU);
111 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
|
| /src/external/cddl/osnet/sys/sys/ |
| proc.h | 72 #define CPU curcpu()
|
| /src/sys/external/bsd/compiler_rt/dist/lib/xray/tests/unit/ |
| fdr_controller_test.cc | 85 uint16_t CPU = 1;
86 ASSERT_TRUE(C->functionEnter(FId, TSC++, CPU));
87 ASSERT_TRUE(C->functionExit(FId, TSC++, CPU));
88 ASSERT_TRUE(C->functionEnterArg(FId, TSC++, CPU, 1));
89 ASSERT_TRUE(C->functionTailExit(FId, TSC++, CPU));
144 uint16_t CPU = 0;
145 ASSERT_TRUE(C->functionEnter(1, TSC++, CPU));
146 ASSERT_TRUE(C->functionEnter(2, TSC++, CPU));
147 ASSERT_TRUE(C->functionExit(2, TSC++, CPU));
148 ASSERT_TRUE(C->functionExit(1, TSC += 1000, CPU));
[all...] |
| function_call_trie_test.cc | 33 uint16_t CPU = 0;
34 Trie.enterFunction(1, TSC++, CPU++);
35 Trie.exitFunction(1, TSC++, CPU++);
217 // TODO: Test that we can handle cross-CPU migrations, where TSCs are not
|
| /src/sys/external/bsd/compiler_rt/dist/include/xray/ |
| xray_records.h | 79 // The CPU where the thread is running. We assume number of CPUs <= 256.
80 uint8_t CPU = 0;
|
| /src/external/apache2/llvm/dist/clang/include/clang/Basic/ |
| TargetOptions.h | 35 /// If given, the name of the target CPU to generate code for.
36 std::string CPU;
38 /// If given, the name of the target CPU to tune code for.
|
| /src/external/apache2/llvm/dist/clang/lib/Driver/ToolChains/ |
| AVR.cpp | 317 std::string CPU = getCPUName(Args, Triple);
319 if (CPU.empty()) {
323 Optional<StringRef> FamilyName = GetMCUFamilyName(CPU);
327 // We do not have an entry for this CPU in the family
330 << CPU;
341 std::string SubPath = GetMCUSubPath(CPU);
365 std::string CPU = getCPUName(Args, getToolChain().getTriple());
366 llvm::Optional<StringRef> FamilyName = GetMCUFamilyName(CPU);
367 llvm::Optional<unsigned> SectionAddressData = GetMCUSectionAddressData(CPU);
388 // We do not have an entry for this CPU in the address mapping table yet
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/XRay/ |
| XRayRecord.h | 35 /// Whether the CPU that produced the timestamp counters (TSC) move at a
39 /// Whether the CPU that produced the timestamp counters (TSC) do not stop.
42 /// The number of cycles per second for the CPU that produced the timestamp
76 /// The CPU where the thread is running. We assume number of CPUs <= 65536.
77 uint16_t CPU;
|
