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    Searched defs:D16 (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
ARMTargetParser.h 151 D16, ///< Only 16 D registers
  /src/lib/libm/ld128/
s_expl.c 188 * With my coeffs (D11-D16 double):
195 D16 = 4.7628892832607741e-14, /* 0x1.ad00Dfe41feccp-45 */
252 dx * (D14 + dx * (D15 + dx * (D16 +
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 694 AMDGPU::OpName::d16);
747 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
748 if (D16 && AMDGPU::hasPackedD16(STI)) {
  /src/external/gpl3/binutils/dist/opcodes/
v850-opc.c 1194 #define D16 (I16U + 1)
1198 #define D16_16 (D16 + 1)
1451 { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1574 { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL },
1648 { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1704 { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1738 { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL },
1788 { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
  /src/external/gpl3/binutils.old/dist/opcodes/
v850-opc.c 1194 #define D16 (I16U + 1)
1198 #define D16_16 (D16 + 1)
1451 { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1574 { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL },
1648 { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1704 { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1738 { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL },
1788 { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
  /src/external/gpl3/gdb/dist/opcodes/
v850-opc.c 1194 #define D16 (I16U + 1)
1198 #define D16_16 (D16 + 1)
1451 { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1574 { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL },
1648 { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1704 { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1738 { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL },
1788 { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
  /src/external/gpl3/gdb.old/dist/opcodes/
v850-opc.c 1194 #define D16 (I16U + 1)
1198 #define D16_16 (D16 + 1)
1451 { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1574 { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL },
1648 { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1704 { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1738 { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL },
1788 { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 3938 const MachineOperand *D16 = getNamedOperand(MI, AMDGPU::OpName::d16);
3941 if (D16 && D16->getImm() && !ST.hasUnpackedD16VMem())
7529 // Adjust the encoding family to GFX80 for D16 buffer instructions when the
SIISelLowering.cpp 4561 // Used for D16: Casts the result of an instruction into the right vector,
4570 // multiple of 32 bit for D16. Widening the return type is a required for
6019 return Op; // D16 is unsupported for this instruction
6032 return Op; // D16 is unsupported for this instruction
6043 // for d16 image_gather4, image_gather4_l, and image_gather4_lz
7461 // No change for f16 and legal vector D16 types.
7479 // The sq block of gfx8.1 does not estimate register use correctly for d16
7481 // d16 image instruction.
10961 int D16Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::d16) - 1;
10963 return Node; // not implemented for D16
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