1 /* $NetBSD: tc_3000_300.c,v 1.39 2021/05/07 16:58:34 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(0, "$NetBSD: tc_3000_300.c,v 1.39 2021/05/07 16:58:34 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/kmem.h> 38 #include <sys/cpu.h> 39 40 #include <machine/autoconf.h> 41 #include <machine/pte.h> 42 43 #include <dev/tc/tcvar.h> 44 #include <dev/tc/ioasicreg.h> 45 #include <alpha/tc/tc_conf.h> 46 #include <alpha/tc/tc_3000_300.h> 47 48 #include "wsdisplay.h" 49 #include "sfb.h" 50 51 #if NSFB > 0 52 extern int sfb_cnattach(tc_addr_t); 53 #endif 54 55 static int tc_3000_300_intrnull(void *); 56 57 #define C(x) ((void *)(u_long)x) 58 #define KV(x) (ALPHA_PHYS_TO_K0SEG(x)) 59 60 /* 61 * We have to read and modify the IOASIC registers directly, because 62 * the TC option slot interrupt request and mask bits are stored there, 63 * and the ioasic code isn't initted when we need to frob some interrupt 64 * bits. 65 */ 66 #define DEC_3000_300_IOASIC_ADDR KV(0x1a0000000) 67 68 const struct tc_slotdesc tc_3000_300_slots[] = { 69 { KV(0x100000000), C(TC_3000_300_DEV_OPT0), }, /* 0 - opt slot 0 */ 70 { KV(0x120000000), C(TC_3000_300_DEV_OPT1), }, /* 1 - opt slot 1 */ 71 { KV(0x140000000), C(TC_3000_300_DEV_BOGUS), }, /* 2 - unused */ 72 { KV(0x160000000), C(TC_3000_300_DEV_BOGUS), }, /* 3 - unused */ 73 { KV(0x180000000), C(TC_3000_300_DEV_BOGUS), }, /* 4 - TCDS ASIC */ 74 { KV(0x1a0000000), C(TC_3000_300_DEV_BOGUS), }, /* 5 - IOCTL ASIC */ 75 { KV(0x1c0000000), C(TC_3000_300_DEV_BOGUS), }, /* 6 - CXTurbo */ 76 }; 77 const int tc_3000_300_nslots = __arraycount(tc_3000_300_slots); 78 79 const struct tc_builtin tc_3000_300_builtins[] = { 80 { "PMAGB-BA", 6, 0x02000000, C(TC_3000_300_DEV_CXTURBO), }, 81 { "FLAMG-IO", 5, 0x00000000, C(TC_3000_300_DEV_IOASIC), }, 82 { "PMAZ-DS ", 4, 0x00000000, C(TC_3000_300_DEV_TCDS), }, 83 }; 84 const int tc_3000_300_nbuiltins = __arraycount(tc_3000_300_builtins); 85 86 static struct tcintr { 87 int (*tci_func)(void *); 88 void *tci_arg; 89 struct evcnt tci_evcnt; 90 } tc_3000_300_intr[TC_3000_300_NCOOKIES]; 91 92 void 93 tc_3000_300_intr_setup(void) 94 { 95 volatile uint32_t *imskp; 96 char *cp; 97 u_long i; 98 99 /* 100 * Disable all interrupts that we can (can't disable builtins). 101 */ 102 imskp = (volatile uint32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK); 103 *imskp &= ~(IOASIC_INTR_300_OPT0 | IOASIC_INTR_300_OPT1); 104 105 /* 106 * Set up interrupt handlers. 107 */ 108 for (i = 0; i < TC_3000_300_NCOOKIES; i++) { 109 tc_3000_300_intr[i].tci_func = tc_3000_300_intrnull; 110 tc_3000_300_intr[i].tci_arg = (void *)i; 111 112 cp = kmem_asprintf("slot %lu", i); 113 evcnt_attach_dynamic(&tc_3000_300_intr[i].tci_evcnt, 114 EVCNT_TYPE_INTR, NULL, "tc", cp); 115 } 116 } 117 118 const struct evcnt * 119 tc_3000_300_intr_evcnt(device_t tcadev, void *cookie) 120 { 121 u_long dev = (u_long)cookie; 122 123 #ifdef DIAGNOSTIC 124 /* XXX bounds-check cookie. */ 125 #endif 126 127 return (&tc_3000_300_intr[dev].tci_evcnt); 128 } 129 130 void 131 tc_3000_300_intr_establish(device_t tcadev, void *cookie, tc_intrlevel_t level, int (*func)(void *), void *arg) 132 { 133 volatile uint32_t *imskp; 134 u_long dev = (u_long)cookie; 135 136 #ifdef DIAGNOSTIC 137 /* XXX bounds-check cookie. */ 138 #endif 139 140 if (tc_3000_300_intr[dev].tci_func != tc_3000_300_intrnull) 141 panic("tc_3000_300_intr_establish: cookie %lu twice", dev); 142 143 const int s = splhigh(); 144 145 /* All TC systems are uniprocessors. */ 146 KASSERT(CPU_IS_PRIMARY(curcpu())); 147 KASSERT(ncpu == 1); 148 curcpu()->ci_nintrhand++; 149 150 tc_3000_300_intr[dev].tci_func = func; 151 tc_3000_300_intr[dev].tci_arg = arg; 152 153 splx(s); 154 155 imskp = (volatile uint32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK); 156 switch (dev) { 157 case TC_3000_300_DEV_OPT0: 158 *imskp |= IOASIC_INTR_300_OPT0; 159 break; 160 case TC_3000_300_DEV_OPT1: 161 *imskp |= IOASIC_INTR_300_OPT1; 162 break; 163 default: 164 /* interrupts for builtins always enabled */ 165 break; 166 } 167 } 168 169 void 170 tc_3000_300_intr_disestablish(device_t tcadev, void *cookie) 171 { 172 volatile uint32_t *imskp; 173 u_long dev = (u_long)cookie; 174 175 #ifdef DIAGNOSTIC 176 /* XXX bounds-check cookie. */ 177 #endif 178 179 if (tc_3000_300_intr[dev].tci_func == tc_3000_300_intrnull) 180 panic("tc_3000_300_intr_disestablish: cookie %lu bad intr", 181 dev); 182 183 imskp = (volatile uint32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK); 184 switch (dev) { 185 case TC_3000_300_DEV_OPT0: 186 *imskp &= ~IOASIC_INTR_300_OPT0; 187 break; 188 case TC_3000_300_DEV_OPT1: 189 *imskp &= ~IOASIC_INTR_300_OPT1; 190 break; 191 default: 192 /* interrupts for builtins always enabled */ 193 break; 194 } 195 196 const int s = splhigh(); 197 198 curcpu()->ci_nintrhand--; 199 200 tc_3000_300_intr[dev].tci_func = tc_3000_300_intrnull; 201 tc_3000_300_intr[dev].tci_arg = (void *)dev; 202 203 splx(s); 204 } 205 206 static int 207 tc_3000_300_intrnull(void *val) 208 { 209 210 panic("tc_3000_300_intrnull: uncaught TC intr for cookie %ld", 211 (u_long)val); 212 } 213 214 void 215 tc_3000_300_iointr(void *arg, unsigned long vec) 216 { 217 uint32_t tcir, ioasicir, ioasicimr; 218 int ifound; 219 220 KERNEL_LOCK(1, NULL); 221 222 #ifdef DIAGNOSTIC 223 int s; 224 if (vec != 0x800) 225 panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec); 226 s = splhigh(); 227 if (s != ALPHA_PSL_IPL_IO_HI) 228 panic("INVALID ASSUMPTION: IPL %d, not %d", s, 229 ALPHA_PSL_IPL_IO_HI); 230 splx(s); 231 #endif 232 233 do { 234 tc_syncbus(); 235 236 /* find out what interrupts/errors occurred */ 237 tcir = *(volatile uint32_t *)TC_3000_300_IR; 238 ioasicir = *(volatile uint32_t *) 239 (DEC_3000_300_IOASIC_ADDR + IOASIC_INTR); 240 ioasicimr = *(volatile uint32_t *) 241 (DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK); 242 tc_mb(); 243 244 /* Ignore interrupts that aren't enabled out. */ 245 ioasicir &= ioasicimr; 246 247 /* clear the interrupts/errors we found. */ 248 *(volatile uint32_t *)TC_3000_300_IR = tcir; 249 /* XXX can't clear TC option slot interrupts here? */ 250 tc_wmb(); 251 252 ifound = 0; 253 254 #define INCRINTRCNT(slot) tc_3000_300_intr[slot].tci_evcnt.ev_count++ 255 256 #define CHECKINTR(slot, flag) \ 257 if (flag) { \ 258 ifound = 1; \ 259 INCRINTRCNT(slot); \ 260 (*tc_3000_300_intr[slot].tci_func) \ 261 (tc_3000_300_intr[slot].tci_arg); \ 262 } 263 /* Do them in order of priority; highest slot # first. */ 264 CHECKINTR(TC_3000_300_DEV_CXTURBO, 265 tcir & TC_3000_300_IR_CXTURBO); 266 CHECKINTR(TC_3000_300_DEV_IOASIC, 267 (tcir & TC_3000_300_IR_IOASIC) && 268 (ioasicir & ~(IOASIC_INTR_300_OPT1|IOASIC_INTR_300_OPT0))); 269 CHECKINTR(TC_3000_300_DEV_TCDS, tcir & TC_3000_300_IR_TCDS); 270 CHECKINTR(TC_3000_300_DEV_OPT1, 271 ioasicir & IOASIC_INTR_300_OPT1); 272 CHECKINTR(TC_3000_300_DEV_OPT0, 273 ioasicir & IOASIC_INTR_300_OPT0); 274 #undef CHECKINTR 275 276 #ifdef DIAGNOSTIC 277 #define PRINTINTR(msg, bits) \ 278 if (tcir & bits) \ 279 printf(msg); 280 PRINTINTR("BCache tag parity error\n", 281 TC_3000_300_IR_BCTAGPARITY); 282 PRINTINTR("TC overrun error\n", TC_3000_300_IR_TCOVERRUN); 283 PRINTINTR("TC I/O timeout\n", TC_3000_300_IR_TCTIMEOUT); 284 PRINTINTR("Bcache parity error\n", 285 TC_3000_300_IR_BCACHEPARITY); 286 PRINTINTR("Memory parity error\n", TC_3000_300_IR_MEMPARITY); 287 #undef PRINTINTR 288 #endif 289 } while (ifound); 290 291 KERNEL_UNLOCK_ONE(NULL); 292 } 293 294 #if NWSDISPLAY > 0 295 /* 296 * tc_3000_300_fb_cnattach -- 297 * Attempt to map the CTB output device to a slot and attach the 298 * framebuffer as the output side of the console. 299 */ 300 int 301 tc_3000_300_fb_cnattach(uint64_t turbo_slot) 302 { 303 uint32_t output_slot; 304 305 output_slot = turbo_slot & 0xffffffff; 306 307 if (output_slot >= tc_3000_300_nslots) { 308 return EINVAL; 309 } 310 311 if (output_slot == 0) { 312 #if NSFB > 0 313 sfb_cnattach(KV(0x1c0000000) + 0x02000000); 314 return 0; 315 #else 316 return ENXIO; 317 #endif 318 } 319 320 return tc_fb_cnattach(tc_3000_300_slots[output_slot-1].tcs_addr); 321 } 322 #endif /* NWSDISPLAY */ 323
Indexes created Thu Oct 02 10:09:58 GMT 2025