| /src/lib/libc/quad/TESTS/ |
| Makefile | 4 all: mul divrem
10 DIVREM= divrem.c ../qdivrem.c
11 divrem: ${DIVREM}
12 gcc -g -DSPARC_XXX ${DIVREM} -o $@
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| arc-tbl.h | 3902 { "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
3905 { "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
3908 { "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
3920 { "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
3923 { "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
3926 { "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
3938 { "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
3944 { "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
3947 { "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
3950 { "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }}
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| arc-tbl.h | 3902 { "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
3905 { "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
3908 { "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
3920 { "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
3923 { "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
3926 { "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
3938 { "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
3944 { "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
3947 { "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
3950 { "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }}
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| arc-tbl.h | 3902 { "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
3905 { "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
3908 { "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
3920 { "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
3923 { "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
3926 { "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
3938 { "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
3944 { "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
3947 { "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
3950 { "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }}
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| arc-tbl.h | 3902 { "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
3905 { "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
3908 { "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
3920 { "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
3923 { "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
3926 { "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
3938 { "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
3944 { "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
3947 { "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
3950 { "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }}
[all...] |
| /src/external/gpl3/binutils/dist/include/opcode/ |
| arc.h | 56 DIVREM,
|
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| arc.h | 56 DIVREM,
|
| /src/external/gpl3/gdb/dist/include/opcode/ |
| arc.h | 56 DIVREM,
|
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| arc.h | 56 DIVREM,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 359 // These should use [SU]DIVREM, so set them to expand
365 // GPU does not have divrem function for signed or unsigned.
2061 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
2064 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
2065 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
|
