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    Searched defs:DR (Results 1 - 25 of 50) sorted by relevancy

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  /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/
CheckerHelpers.cpp 39 const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(S);
41 if (DR && isa<EnumConstantDecl>(DR->getDecl()))
53 const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(S);
55 if (DR)
56 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl()))
  /src/external/gpl3/gdb/dist/sim/bfin/
dv-bfin_uart.h 44 #define DR (1 << 0)
  /src/external/gpl3/gdb.old/dist/sim/bfin/
dv-bfin_uart.h 44 #define DR (1 << 0)
  /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/
DereferenceChecker.cpp 67 const DeclRefExpr *DR = cast<DeclRefExpr>(Ex);
68 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) {
71 Ranges.push_back(DR->getSourceRange());
DeadStoresChecker.cpp 55 bool VisitDeclRefExpr(DeclRefExpr *DR) {
57 if (const VarDecl *D = dyn_cast<VarDecl>(DR->getDecl()))
289 void CheckDeclRef(const DeclRefExpr *DR, const Expr *Val, DeadStoreKind dsk,
291 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl()))
292 CheckVarDecl(VD, DR, Val, dsk, Live);
305 const DeclRefExpr *DR;
307 if ((DR = dyn_cast<DeclRefExpr>(BRHS->getLHS()->IgnoreParenCasts())))
308 if (DR->getDecl() == VD)
311 if ((DR = dyn_cast<DeclRefExpr>(BRHS->getRHS()->IgnoreParenCasts())))
312 if (DR->getDecl() == VD
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/ADT/
iterator.h 366 const DataRef DR;
370 WrappedPairNodeDataIterator(ItType Begin, const DataRef DR)
371 : BaseT(Begin), DR(DR) {
372 NR.first = DR;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
RDFCopy.cpp 145 RegisterRef DR = DA.Addr->getRegRef(DFG);
146 auto FR = EM.find(DR);
150 if (DR == SR)
161 if (UA.Addr->getRegRef(DFG) != DR)
174 dbgs() << "Can replace " << Print<RegisterRef>(DR, DFG)
202 if (J.second != DR)
HexagonGenPredicate.cpp 474 RegisterSubReg DR = MI.getOperand(0);
476 if (!DR.R.isVirtual())
480 if (MRI->getRegClass(DR.R) != PredRC)
484 assert(!DR.S && !SR.S && "Unexpected subregister");
485 MRI->replaceRegWith(DR.R, SR.R);
HexagonGenMux.cpp 112 MuxInfo(MachineBasicBlock::iterator It, unsigned DR, unsigned PR,
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1),
242 Register DR = MI->getOperand(0).getReg();
243 if (isRegPair(DR))
251 CondsetMap::iterator F = CM.find(DR);
261 auto It = CM.insert(std::make_pair(DR, CondsetInfo()));
274 // There is now a complete definition of DR, i.e. we have the predicate
311 if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) {
328 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2))
    [all...]
HexagonOptAddrMode.cpp 249 RegisterRef DR = DA.Addr->getRegRef(*DFG);
251 auto UseSet = LV->getAllReachedUses(DR, DA);
269 if (!DFG->getPRI().alias(RegisterRef(I.first), DR))
  /src/external/apache2/llvm/dist/clang/lib/Analysis/
LiveVariables.cpp 166 void VisitDeclRefExpr(DeclRefExpr *DR);
329 if (const auto *DR = dyn_cast<DeclRefExpr>(B->getLHS()->IgnoreParens())) {
330 LV.inAssignment[DR] = 1;
340 if (DeclRefExpr *DR = dyn_cast<DeclRefExpr>(LHS)) {
341 const Decl* D = DR->getDecl();
356 observer->observerKill(DR);
370 void TransferFunctions::VisitDeclRefExpr(DeclRefExpr *DR) {
371 const Decl* D = DR->getDecl();
372 bool InAssignment = LV.inAssignment[DR];
396 DeclRefExpr *DR = nullptr
    [all...]
ReachableCode.cpp 35 const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(Ex);
36 if (!DR)
38 return isa<EnumConstantDecl>(DR->getDecl());
BodyFarm.cpp 141 DeclRefExpr *DR = DeclRefExpr::Create(
144 return DR;
581 DeclRefExpr *DR = M.makeDeclRefExpr(PV);
582 ImplicitCastExpr *ICE = M.makeLvalueToRvalue(DR, Ty);
  /src/external/gpl3/binutils/dist/opcodes/
msp430-decode.c 82 #define DR(r) OP (0, MSP430_Operand_Register, r, 0)
189 DR (reg);
378 ID (MSO_mov); SM (srcr, 0); DR (dstr);
402 ID (MSO_mov); SI (srcr); DR (dstr);
426 ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr);
450 ID (MSO_mov); SM (srcr, IMMS(2)); DR (dstr);
478 ID (MSO_rrc); DR (dstr); SR (dstr);
552 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
576 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr);
601 ID (MSO_add); SC ((srcr << 16) + IMMU(2)); DR (dstr)
    [all...]
rl78-decode.c 116 #define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0)
123 #define DCY() DR(PSW); DB(0)
235 ID(add); W(); DR(AX); SRW(rw); Fzac;
250 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
265 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
280 ID(add); W(); DR(AX); SM(None, SADDR); Fzac;
295 ID(xch); DR(A); SR(X);
312 ID(mov); DR(A); SM(B, IMMU(2));
344 ID(add); DR(A); SM(None, SADDR); Fzac;
359 ID(add); DR(A); SC(IMMU(1)); Fzac
    [all...]
rx-decode.c 120 #define DR(r) OP (0, RX_Operand_Register, r, 0)
441 ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC;
566 ID(add); SPm(ss, rsrc, mx); DR(rdst); F_OSZC;
627 ID(mul); SPm(ss, rsrc, mx); DR(rdst); F_____;
688 ID(and); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
749 ID(or); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
814 ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F_OSZC;
851 ID(max); SPm(ss, rsrc, mx); DR(rdst);
888 ID(min); SPm(ss, rsrc, mx); DR(rdst);
925 ID(emul); SPm(ss, rsrc, mx); DR(rdst)
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
msp430-decode.c 82 #define DR(r) OP (0, MSP430_Operand_Register, r, 0)
189 DR (reg);
378 ID (MSO_mov); SM (srcr, 0); DR (dstr);
402 ID (MSO_mov); SI (srcr); DR (dstr);
426 ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr);
450 ID (MSO_mov); SM (srcr, IMMS(2)); DR (dstr);
478 ID (MSO_rrc); DR (dstr); SR (dstr);
552 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
576 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr);
601 ID (MSO_add); SC ((srcr << 16) + IMMU(2)); DR (dstr)
    [all...]
rl78-decode.c 116 #define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0)
123 #define DCY() DR(PSW); DB(0)
235 ID(add); W(); DR(AX); SRW(rw); Fzac;
250 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
265 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
280 ID(add); W(); DR(AX); SM(None, SADDR); Fzac;
295 ID(xch); DR(A); SR(X);
312 ID(mov); DR(A); SM(B, IMMU(2));
344 ID(add); DR(A); SM(None, SADDR); Fzac;
359 ID(add); DR(A); SC(IMMU(1)); Fzac
    [all...]
rx-decode.c 120 #define DR(r) OP (0, RX_Operand_Register, r, 0)
441 ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC;
566 ID(add); SPm(ss, rsrc, mx); DR(rdst); F_OSZC;
627 ID(mul); SPm(ss, rsrc, mx); DR(rdst); F_____;
688 ID(and); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
749 ID(or); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
814 ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F_OSZC;
851 ID(max); SPm(ss, rsrc, mx); DR(rdst);
888 ID(min); SPm(ss, rsrc, mx); DR(rdst);
925 ID(emul); SPm(ss, rsrc, mx); DR(rdst)
    [all...]
  /src/external/gpl3/gdb/dist/opcodes/
msp430-decode.c 82 #define DR(r) OP (0, MSP430_Operand_Register, r, 0)
189 DR (reg);
378 ID (MSO_mov); SM (srcr, 0); DR (dstr);
402 ID (MSO_mov); SI (srcr); DR (dstr);
426 ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr);
450 ID (MSO_mov); SM (srcr, IMMS(2)); DR (dstr);
478 ID (MSO_rrc); DR (dstr); SR (dstr);
552 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
576 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr);
601 ID (MSO_add); SC ((srcr << 16) + IMMU(2)); DR (dstr)
    [all...]
rl78-decode.c 116 #define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0)
123 #define DCY() DR(PSW); DB(0)
235 ID(add); W(); DR(AX); SRW(rw); Fzac;
250 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
265 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
280 ID(add); W(); DR(AX); SM(None, SADDR); Fzac;
295 ID(xch); DR(A); SR(X);
312 ID(mov); DR(A); SM(B, IMMU(2));
344 ID(add); DR(A); SM(None, SADDR); Fzac;
359 ID(add); DR(A); SC(IMMU(1)); Fzac
    [all...]
rx-decode.c 120 #define DR(r) OP (0, RX_Operand_Register, r, 0)
441 ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC;
566 ID(add); SPm(ss, rsrc, mx); DR(rdst); F_OSZC;
627 ID(mul); SPm(ss, rsrc, mx); DR(rdst); F_____;
688 ID(and); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
749 ID(or); SPm(ss, rsrc, mx); DR(rdst); F__SZ_;
814 ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F_OSZC;
851 ID(max); SPm(ss, rsrc, mx); DR(rdst);
888 ID(min); SPm(ss, rsrc, mx); DR(rdst);
925 ID(emul); SPm(ss, rsrc, mx); DR(rdst)
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
msp430-decode.c 82 #define DR(r) OP (0, MSP430_Operand_Register, r, 0)
189 DR (reg);
378 ID (MSO_mov); SM (srcr, 0); DR (dstr);
402 ID (MSO_mov); SI (srcr); DR (dstr);
426 ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr);
450 ID (MSO_mov); SM (srcr, IMMS(2)); DR (dstr);
478 ID (MSO_rrc); DR (dstr); SR (dstr);
552 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
576 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr);
601 ID (MSO_add); SC ((srcr << 16) + IMMU(2)); DR (dstr)
    [all...]
rl78-decode.c 116 #define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0)
123 #define DCY() DR(PSW); DB(0)
235 ID(add); W(); DR(AX); SRW(rw); Fzac;
250 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
265 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
280 ID(add); W(); DR(AX); SM(None, SADDR); Fzac;
295 ID(xch); DR(A); SR(X);
312 ID(mov); DR(A); SM(B, IMMU(2));
344 ID(add); DR(A); SM(None, SADDR); Fzac;
359 ID(add); DR(A); SC(IMMU(1)); Fzac
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RDFLiveness.cpp 446 RegisterRef DR = DA.Addr->getRegRef(DFG);
449 if (DefRRs.hasCoverOf(DR) || !PRI.alias(RefRR, DR))
457 NewDefRRs.insert(DR);

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