| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUGlobalISelUtils.cpp | 18 MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
19 if (!Def)
22 if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
24 const MachineOperand &Op = Def->getOperand(1);
34 if (Def->getOpcode() == TargetOpcode::G_ADD) {
36 if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
37 return std::make_pair(Def->getOperand(1).getReg(), Offset);
40 if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
41 return std::make_pair(Def->getOperand(1).getReg(), Offset);
45 if (Def->getOpcode() == TargetOpcode::G_PTRTOINT)
[all...] |
| GCNNSAReassign.cpp | 201 const MachineInstr *Def = MRI->getUniqueVRegDef(Reg);
203 if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyLowerBrUnless.cpp | 77 MachineInstr *Def = MRI.getVRegDef(Cond);
78 switch (Def->getOpcode()) {
81 Def->setDesc(TII.get(NE_I32));
85 Def->setDesc(TII.get(EQ_I32));
89 Def->setDesc(TII.get(LE_S_I32));
93 Def->setDesc(TII.get(LT_S_I32));
97 Def->setDesc(TII.get(GE_S_I32));
101 Def->setDesc(TII.get(GT_S_I32));
105 Def->setDesc(TII.get(LE_U_I32));
109 Def->setDesc(TII.get(LT_U_I32))
[all...] |
| WebAssemblyExplicitLocals.cpp | 189 MachineInstr *Def = MRI.getVRegDef(Reg);
192 for (auto DefReg : Def->defs()) {
194 return Def;
199 for (MachineOperand &DefMO : Def->explicit_uses()) {
206 return Def;
267 // instructions have two defs, while local.tee instructions have one def
303 for (auto &Def : MI.defs()) {
304 Register OldReg = Def.getReg();
331 Def.setReg(NewReg);
332 Def.setIsDead(false)
[all...] |
| WebAssemblyRegisterInfo.cpp | 96 MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg);
98 // the CONST_I32/64 happens to have exactly one def and one use. We
100 if (Def && Def->getOpcode() ==
102 MRI.hasOneNonDBGUse(Def->getOperand(0).getReg())) {
103 MachineOperand &ImmMO = Def->getOperand(1);
|
| /src/external/apache2/llvm/dist/llvm/lib/TableGen/ |
| JSONBackend.cpp | 76 if (auto *Def = dyn_cast<DefInit>(&I)) {
77 obj["kind"] = "def";
78 obj["def"] = Def->getDef()->getName();
126 // each def, but we also want to ensure we store an empty list for a
139 auto &Def = *D.second;
144 for (const RecordVal &RV : Def.getValues()) {
145 if (!Def.isTemplateArg(RV.getNameInit())) {
156 for (const auto &SuperPair : Def.getSuperClasses())
161 obj["!anonymous"] = Def.isAnonymous()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/ToolDrivers/llvm-dlltool/ |
| DlltoolDriver.cpp | 131 Expected<COFFModuleDefinition> Def =
134 if (!Def) {
136 << errorToErrorCode(Def.takeError()).message();
142 Def->OutputFile = Arg->getValue();
144 if (Def->OutputFile.empty()) {
156 for (COFFShortExport& E : Def->Exports) {
164 for (COFFShortExport& E : Def->Exports) {
181 writeImportLibrary(Def->OutputFile, Path, Def->Exports, Machine, true))
|
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| MemDepPrinter.cpp | 31 Def,
69 return InstTypePair(dep.getInst(), Def);
90 = {"Clobber", "Def", "NonFuncLocal", "Unknown"};
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| UnifyLoopExits.cpp | 68 // SSA requirement that every def must dominate all its uses. For example,
109 // For each Def used outside the loop, create NewPhi in
110 // LoopExitBlock. NewPhi receives Def only along exiting blocks that
113 auto Def = II.first;
114 LLVM_DEBUG(dbgs() << "externally used: " << Def->getName() << "\n");
115 auto NewPhi = PHINode::Create(Def->getType(), Incoming.size(),
116 Def->getName() + ".moved",
120 if (Def->getParent() == In || DT.dominates(Def, In)) {
122 NewPhi->addIncoming(Def, In)
[all...] |
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| WebAssemblyDisassemblerEmitter.cpp | 33 auto &Def = *CGI.TheDef;
34 if (!Def.getValue("Inst"))
36 auto &Inst = *Def.getValueAsBitsInit("Inst");
55 Def.getValue("StackBased")->getValue()->getCastTo(StringRecTy::get());
73 Def.getValue("IsCanonical")->getValue()->getAsString() == "1";
|
| /src/external/apache2/llvm/dist/clang/lib/Format/ |
| MacroExpander.cpp | 61 Def.Name = Current->TokenText;
64 Def.ObjectLike = false;
71 return Def;
79 Def.Params.push_back(Current);
80 Def.ArgMap[Def.Params.back()->TokenText] = Def.Params.size() - 1;
103 Def.Body.push_back(Current);
106 Def.Body.push_back(Current);
118 Definition Def;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| LiveInterval.cpp | 77 /// value defined at @p Def.
78 /// If @p ForVNI is null, and there is no value defined at @p Def, a new
80 /// If @p ForVNI is null, the return value is the value defined at @p Def,
82 /// If @p ForVNI is not null, then @p Def should be the location where
84 /// @p Def, the value @p ForVNI will be used instead of allocating a new
85 /// one. If the range already has a value defined at @p Def, it must be
87 VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator *VNInfoAllocator,
89 assert(!Def.isDead() && "Cannot define a value at the dead slot");
90 assert((!ForVNI || ForVNI->def == Def) &
[all...] |
| ReachingDefAnalysis.cpp | 1 //===---- ReachingDefAnalysis.cpp - Reaching Def Analysis ---*- C++ -*-----===//
105 // While processing the basic block, we kept `Def` relative to the start
163 int Def = Incoming[Unit];
164 if (Def == ReachingDefDefaultVal)
169 if (*Start >= Def)
172 // Update existing reaching def from predecessor to a more recent one.
173 *Start = Def;
175 // Insert new reaching def from predecessor.
176 MBBReachingDefs[MBBNumber][Unit].insert(Start, Def);
179 // Update reaching def at end of of BB. Keep in mind that these ar
[all...] |
| MIRCanonicalizerPass.cpp | 215 MachineInstr *Def = II;
222 const unsigned DefLoc = getInstrIdx(*Def);
226 if (UseInst->getParent() != Def->getParent())
247 if (&*BBI == Def) {
268 MultiUsers[UseToBringDefCloserTo].push_back(Def);
|
| RenameIndependentSubregs.cpp | 311 // There must be a def (or live-in) before every use. Splitting vregs may
323 SlotIndex Def = VNI.def;
324 MachineBasicBlock &MBB = *Indexes.getMBBFromIndex(Def);
369 // A def of a subregister may be a use of other register lanes. Replacing
370 // such a def with a def of a different register will eliminate the use,
|
| DetectDeadLanes.cpp | 74 /// Given a bitmask \p UsedLanes for the used lanes on a def output of a
81 /// mask to the def and put the instruction into the worklist.
87 /// operand \p Def.
88 LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
249 const MachineOperand &Def = MI.getOperand(0);
250 Register DefReg = Def.getReg();
280 // FIXME: PATCHPOINT instructions announce a Def that does not always exist,
284 const MachineOperand &Def = *MI.defs().begin();
285 Register DefReg = Def.getReg();
295 DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| Dominators.cpp | 125 // dominates - Return true if Def dominates a use in User. This performs
126 // the special checks necessary if Def and User are in the same basic block.
127 // Note that Def doesn't dominate a use in Def itself!
130 const Instruction *Def = dyn_cast<Instruction>(DefV);
131 if (!Def) {
138 const BasicBlock *DefBB = Def->getParent();
140 // Any unreachable use is dominated, even if Def == User.
149 if (Def == User)
156 if (isa<InvokeInst>(Def) || isa<CallBrInst>(Def) || isa<PHINode>(User)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86WinAllocaExpander.cpp | 86 MachineInstr *Def = MRI->getUniqueVRegDef(AmountReg);
88 if (!Def ||
89 (Def->getOpcode() != X86::MOV32ri && Def->getOpcode() != X86::MOV64ri) ||
90 !Def->getOperand(1).isImm())
93 return Def->getOperand(1).getImm();
|
| /src/external/apache2/llvm/dist/clang/lib/Lex/ |
| PreprocessingRecord.cpp | 345 MacroDefinitionRecord *Def) {
346 MacroDefinitions[Macro] = Def;
402 else if (MacroDefinitionRecord *Def = findMacroDefinition(MI))
403 addPreprocessedEntity(new (*this) MacroExpansion(Def, Range));
448 MacroDefinitionRecord *Def =
450 addPreprocessedEntity(Def);
451 MacroDefinitions[MI] = Def;
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| MemoryDependenceAnalysis.h | 84 /// that the def may not be the same type as the query, the pointers
89 /// 3. Dependence queries on calls return Def only when they are readonly
93 Def,
121 PointerSumTypeMember<Def, Instruction *>,
133 assert(Inst && "Def requires inst");
134 return MemDepResult(ValueTy::create<Def>(Inst));
156 bool isDef() const { return Value.is<Def>(); }
184 case Def:
185 return Value.cast<Def>();
315 /// Cache storing single nonlocal def for the instruction
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/TableGen/ |
| DirectiveEmitter.h | 16 Def = DirectiveLanguages[0];
19 StringRef getName() const { return Def->getValueAsString("name"); }
22 return Def->getValueAsString("cppNamespace");
26 return Def->getValueAsString("directivePrefix");
30 return Def->getValueAsString("clausePrefix");
34 return Def->getValueAsString("clauseEnumSetClass");
38 return Def->getValueAsString("flangClauseBaseClass");
42 return Def->getValueAsBit("makeEnumAvailableInNamespace");
46 return Def->getValueAsBit("enableBitmaskEnumInNamespace");
60 const llvm::Record *Def;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 209 MachineRegisterInfo::def_instr_iterator Def =
211 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
212 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0);
222 MachineRegisterInfo::def_instr_iterator Def =
224 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
225 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1);
302 MachineRegisterInfo::def_instr_iterator Def =
304 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!")
[all...] |
| AArch64CollectLOH.cpp | 173 /// Answer the following question: Can Def be one of the definition
399 // def register of the ADD may have a use in between. Adding an LOH in
426 // [x0 = some other def]
431 // [x0 = some other def]
569 const MachineOperand &Def = MI.getOperand(0);
571 assert(Def.isReg() && Def.isDef() && "Expected reg def");
573 int DefIdx = mapRegToGPRIndex(Def.getReg());
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| VPlanValue.h | 40 // This is the base class of the VPlan Def/Use graph, used for modeling the data
65 VPDef *Def;
67 VPValue(const unsigned char SC, Value *UV = nullptr, VPDef *Def = nullptr);
107 VPValue(Value *UV = nullptr, VPDef *Def = nullptr)
108 : VPValue(VPValueSC, UV, Def) {}
174 VPDef *getDef() { return Def; }
191 /// This class augments VPValue with operands which provide the inverse def-use
308 V->Def = nullptr;
338 assert(D->Def == this &&
342 D->Def = nullptr
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| InlineAsmLowering.cpp | 415 // tied operands that can use the regclass information from the def.
436 // Find operand with register def that corresponds to DefIdx.
456 Register Def = Inst->getOperand(DefRegIdx).getReg();
461 // When Def is physreg: use given input.
463 // When Def is vreg: copy input to new vreg with same reg class as Def.
464 if (Def.isVirtual()) {
465 In = MRI->createVirtualRegister(MRI->getRegClass(Def));
470 // Add Flag and input register operand (In) to Inst. Tie In to Def.
|
