| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/MCTargetDesc/ |
| MSP430InstPrinter.cpp | 71 const MCOperand &Disp = MI->getOperand(OpNo+1);
84 if (Disp.isExpr())
85 Disp.getExpr()->print(O, &MAI);
87 assert(Disp.isImm() && "Expected immediate in displacement field");
88 O << Disp.getImm();
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/Disassembler/ |
| PPCDisassembler.cpp | 232 uint64_t Disp = Imm & 0xFFFF;
256 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
267 uint64_t Disp = Imm & 0x3FFF;
277 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
290 const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
294 Inst.addOperand(MCOperand::createImm(Disp));
305 uint64_t Disp = Imm & 0xFFF;
309 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
320 uint64_t Disp = Imm & 0x3FFFFFFFFUL;
324 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430AsmPrinter.cpp | 110 const MachineOperand &Disp = MI->getOperand(OpNum+1);
115 if (Disp.isImm() && Base.getReg() == MSP430::SR)
|
| MSP430ISelDAGToDAG.cpp | 47 int16_t Disp = 0;
70 errs() << " Disp " << Disp << '\n';
119 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
145 AM.Disp += G->getOffset();
150 AM.Disp += CP->getOffset();
187 AM.Disp += Val;
230 AM.Disp += Offset;
245 SDValue &Base, SDValue &Disp) {
262 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(N)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kRegisterInfo.cpp | 172 // NOTE Base contains the FI and we need to backtrace a bit to get Disp
173 MachineOperand &Disp = MI.getOperand(FIOperandNum - 1);
176 int Imm = (int)(Disp.getImm());
209 Disp.ChangeToImmediate(FIOffset + Imm);
|
| M68kISelDAGToDAG.cpp | 63 int64_t Disp;
83 : AM(AT), BaseType(Base::RegBase), Disp(0), BaseFrameIndex(0), IndexReg(),
152 dbgs() << "\nDisp: " << Disp;
228 // If Address Mode represents Frame Index store FI in Disp and
232 SDValue &Disp, SDValue &Base) {
234 Disp = getI32Imm(AM.Disp, DL);
247 Sym = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(), MVT::i32, AM.Disp,
254 AM.Disp, AM.SymbolFlags);
259 assert(!AM.Disp && "Non-zero displacement is ignored with ES.")
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZInstPrinter.cpp | 27 int64_t Disp, unsigned Index,
29 O << Disp;
211 uint64_t Disp = MI->getOperand(OpNum + 1).getImm();
213 O << Disp << '(' << Length;
224 uint64_t Disp = MI->getOperand(OpNum + 1).getImm();
226 O << Disp << "(";
|
| SystemZMCCodeEmitter.cpp | 187 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
188 assert(isUInt<4>(Base) && isUInt<12>(Disp));
189 return (Base << 12) | Disp;
197 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
198 assert(isUInt<4>(Base) && isInt<20>(Disp));
199 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
207 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
209 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
210 return (Index << 16) | (Base << 12) | Disp;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 40 /// with BP or SP and Disp being offsetted accordingly. The displacement may
55 int Disp;
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
81 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
83 MO.push_back(MachineOperand::CreateImm(Disp));
114 AM.Disp = Op3.getImm();
185 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
187 MIB.addImm(AM.Disp);
|
| X86FixupLEAs.cpp | 375 const MachineOperand &Disp = MI.getOperand(1 + X86::AddrDisp);
378 if (Segment.getReg() != 0 || !Disp.isImm() || Scale.getImm() > 1 ||
403 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
426 if (OptIncDec && (Disp.getImm() == 1 || Disp.getImm() == -1)) {
427 bool IsINC = Disp.getImm() == 1;
439 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp);
443 .addReg(BaseReg).addImm(Disp.getImm())
447 .addReg(BaseReg).addImm(Disp.getImm());
|
| X86OptimizeLEAs.cpp | 85 const MachineOperand *Disp)
86 : Disp(Disp) {
103 return isSimilarDispOp(*Disp, *Other.Disp);
110 const MachineOperand *Disp;
136 assert(Val.Disp != PtrInfo::getEmptyKey() && "Cannot hash the empty key");
137 assert(Val.Disp != PtrInfo::getTombstoneKey() &&
147 switch (Val.Disp->getType()) {
152 Hash = hash_combine(Hash, Val.Disp->getIndex())
[all...] |
| X86AvoidStoreForwardingBlocks.cpp | 315 const MachineOperand &Disp = getDispOperand(MI);
322 if (!Disp.isImm())
664 for (auto Disp : DispSizeStack)
665 BlockingStoresDispSizeMap.insert(Disp);
|
| X86ExpandPseudo.cpp | 463 int64_t Disp = MBBI->getOperand(1 + X86::AddrDisp).getImm();
464 assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
478 MIBHi.addImm(Disp + 2);
497 int64_t Disp = MBBI->getOperand(X86::AddrDisp).getImm();
498 assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
510 MIBHi.addImm(Disp + 2);
682 .addImm(/*Disp=*/Offset)
|
| X86FastISel.cpp | 804 // Now construct the final address. Note that the Disp, Scale,
890 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
892 if (isInt<32>(Disp)) {
893 AM.Disp = (uint32_t)Disp;
904 uint64_t Disp = (int32_t)AM.Disp;
915 Disp += SL->getElementOffset(cast<ConstantInt>(Op)->getZExtValue());
925 Disp += CI->getSExtValue() * S
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelDAGToDAG.cpp | 38 bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
65 SDValue &Disp) {
73 Disp = CurDAG->getTargetConstant(0, dl, MVT::i8);
100 Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i16);
112 Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i8);
225 SDValue Base, Disp;
227 if (SelectAddr(Op.getNode(), Op, Base, Disp)) {
229 OutOps.push_back(Disp);
260 SDValue Base, Disp;
279 Disp = CurDAG->getTargetConstant(ImmNode->getAPIntValue().getZExtValue(), dl, MVT::i8)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 546 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp);
548 !Disp.isImm())
553 return Addr + Size + Disp.getImm();
|
| X86MCCodeEmitter.cpp | 68 void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
385 const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
404 if (!(Disp.isExpr() && isa<MCSymbolRefExpr>(Disp.getExpr())))
452 int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags)
456 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, OS,
500 if (Disp.isImm() && isInt<8>(Disp.getImm())) {
501 if (Disp.getImm() == 0 && RMfield != 6) {
508 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, OS, Fixups)
[all...] |
| /src/external/gpl3/binutils/dist/include/opcode/ |
| tic30.h | 198 #define Disp 0x0080
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
264 { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
265 { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
266 { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
267 { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
268 { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
269 { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }
[all...] |
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| tic30.h | 198 #define Disp 0x0080
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
264 { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
265 { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
266 { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
267 { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
268 { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
269 { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }
[all...] |
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| tic30.h | 198 #define Disp 0x0080
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
264 { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
265 { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
266 { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
267 { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
268 { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
269 { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }
[all...] |
| /src/external/gpl3/gdb/dist/include/opcode/ |
| tic30.h | 198 #define Disp 0x0080
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
264 { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
265 { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
266 { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
267 { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
268 { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
269 { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/ |
| X86Operand.h | 59 const MCExpr *Disp;
141 if (Mem.Disp)
142 PrintImmValue(Mem.Disp, ",Disp=");
176 return Mem.Disp;
664 CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
669 Res->Mem.Disp = Disp;
685 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
701 Res->Mem.Disp = Disp
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Object/ |
| XCOFFObjectFile.cpp | 1006 SmallVector<uint32_t, 8> Disp;
1007 Disp.reserve(NumOfCtlAnchors.getValue());
1009 Disp.push_back(DE.getU32(Cur));
1011 ControlledStorageInfoDisp = std::move(Disp);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 110 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
119 const MCExpr *Disp;
185 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
192 Op->Mem.Disp = Disp;
267 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
270 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
307 addExpr(Inst, Mem.Disp);
313 addExpr(Inst, Mem.Disp);
320 addExpr(Inst, Mem.Disp);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 58 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0)
60 int64_t Disp;
65 : Form(form), DR(dr), Base(), Disp(0), Index(),
91 errs() << " Disp " << Disp;
159 SDValue &Base, SDValue &Disp) const;
161 SDValue &Base, SDValue &Disp, SDValue &Index) const;
165 // Base and Disp respectively.
167 SDValue &Base, SDValue &Disp) const;
171 // base and displacement in Base and Disp respectively
[all...] |
