1 /* $NetBSD: isp_pci.c,v 1.123 2026/07/26 23:43:27 thorpej Exp $ */ 2 /* 3 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 4 * All rights reserved. 5 * 6 * Additional Copyright (C) 2000-2007 by Matthew Jacob 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 33 */ 34 35 /* 36 * 24XX 4Gb material support provided by MetrumRG Associates. 37 * Many thanks are due to them. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.123 2026/07/26 23:43:27 thorpej Exp $"); 42 43 #include <dev/ic/isp_netbsd.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 #include <sys/reboot.h> 48 49 static uint32_t isp_pci_rd_reg(struct ispsoftc *, int); 50 static void isp_pci_wr_reg(struct ispsoftc *, int, uint32_t); 51 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 52 static uint32_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 53 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, uint32_t); 54 #endif 55 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 56 !defined(ISP_DISABLE_2200_SUPPORT) && \ 57 !defined(ISP_DISABLE_1020_SUPPORT) && \ 58 !defined(ISP_DISABLE_1080_SUPPORT) && \ 59 !defined(ISP_DISABLE_12160_SUPPORT) 60 static int 61 isp_pci_rd_isr(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 62 #endif 63 #if !(defined(ISP_DISABLE_2300_SUPPORT) && defined(ISP_DISABLE_2322_SUPPORT)) 64 static int 65 isp_pci_rd_isr_2300(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 66 #endif 67 #if !defined(ISP_DISABLE_2400_SUPPORT) 68 static uint32_t isp_pci_rd_reg_2400(struct ispsoftc *, int); 69 static void isp_pci_wr_reg_2400(struct ispsoftc *, int, uint32_t); 70 static int 71 isp_pci_rd_isr_2400(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 72 #endif 73 static int isp_pci_mbxdma(struct ispsoftc *); 74 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, void *); 75 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, uint32_t); 76 static void isp_pci_reset0(struct ispsoftc *); 77 static void isp_pci_reset1(struct ispsoftc *); 78 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 79 static int isp_pci_intr(void *); 80 81 #if defined(ISP_DISABLE_1020_SUPPORT) || defined(ISP_DISABLE_FW) 82 #define ISP_1040_RISC_CODE NULL 83 #else 84 #define ISP_1040_RISC_CODE (const uint16_t *) isp_1040_risc_code 85 #include <dev/microcode/isp/asm_1040.h> 86 #endif 87 88 #if defined(ISP_DISABLE_1080_SUPPORT) || defined(ISP_DISABLE_FW) 89 #define ISP_1080_RISC_CODE NULL 90 #else 91 #define ISP_1080_RISC_CODE (const uint16_t *) isp_1080_risc_code 92 #include <dev/microcode/isp/asm_1080.h> 93 #endif 94 95 #if defined(ISP_DISABLE_12160_SUPPORT) || defined(ISP_DISABLE_FW) 96 #define ISP_12160_RISC_CODE NULL 97 #else 98 #define ISP_12160_RISC_CODE (const uint16_t *) isp_12160_risc_code 99 #include <dev/microcode/isp/asm_12160.h> 100 #endif 101 102 #if defined(ISP_DISABLE_2100_SUPPORT) || defined(ISP_DISABLE_FW) 103 #define ISP_2100_RISC_CODE NULL 104 #else 105 #define ISP_2100_RISC_CODE (const uint16_t *) isp_2100_risc_code 106 #include <dev/microcode/isp/asm_2100.h> 107 #endif 108 109 #if defined(ISP_DISABLE_2200_SUPPORT) || defined(ISP_DISABLE_FW) 110 #define ISP_2200_RISC_CODE NULL 111 #else 112 #define ISP_2200_RISC_CODE (const uint16_t *) isp_2200_risc_code 113 #include <dev/microcode/isp/asm_2200.h> 114 #endif 115 116 #if defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_FW) 117 #define ISP_2300_RISC_CODE NULL 118 #else 119 #define ISP_2300_RISC_CODE (const uint16_t *) isp_2300_risc_code 120 #include <dev/microcode/isp/asm_2300.h> 121 #endif 122 #if defined(ISP_DISABLE_2322_SUPPORT) || defined(ISP_DISABLE_FW) 123 #define ISP_2322_RISC_CODE NULL 124 #else 125 #define ISP_2322_RISC_CODE (const uint16_t *) isp_2322_risc_code 126 #include <dev/microcode/isp/asm_2322.h> 127 #endif 128 129 #if defined(ISP_DISABLE_2400_SUPPORT) || defined(ISP_DISABLE_FW) 130 #define ISP_2400_RISC_CODE NULL 131 #define ISP_2500_RISC_CODE NULL 132 #else 133 #define ISP_2500 134 #define ISP_2400 135 #define ISP_2400_RISC_CODE (const uint32_t *) isp_2400_risc_code 136 #define ISP_2500_RISC_CODE (const uint32_t *) isp_2500_risc_code 137 #include <dev/microcode/isp/asm_2400.h> 138 #include <dev/microcode/isp/asm_2500.h> 139 #endif 140 141 #ifndef ISP_DISABLE_1020_SUPPORT 142 static struct ispmdvec mdvec = { 143 isp_pci_rd_isr, 144 isp_pci_rd_reg, 145 isp_pci_wr_reg, 146 isp_pci_mbxdma, 147 isp_pci_dmasetup, 148 isp_pci_dmateardown, 149 isp_pci_reset0, 150 isp_pci_reset1, 151 isp_pci_dumpregs, 152 ISP_1040_RISC_CODE, 153 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 154 0 155 }; 156 #endif 157 158 #ifndef ISP_DISABLE_1080_SUPPORT 159 static struct ispmdvec mdvec_1080 = { 160 isp_pci_rd_isr, 161 isp_pci_rd_reg_1080, 162 isp_pci_wr_reg_1080, 163 isp_pci_mbxdma, 164 isp_pci_dmasetup, 165 isp_pci_dmateardown, 166 isp_pci_reset0, 167 isp_pci_reset1, 168 isp_pci_dumpregs, 169 ISP_1080_RISC_CODE, 170 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 171 0 172 }; 173 #endif 174 175 #ifndef ISP_DISABLE_12160_SUPPORT 176 static struct ispmdvec mdvec_12160 = { 177 isp_pci_rd_isr, 178 isp_pci_rd_reg_1080, 179 isp_pci_wr_reg_1080, 180 isp_pci_mbxdma, 181 isp_pci_dmasetup, 182 isp_pci_dmateardown, 183 isp_pci_reset0, 184 isp_pci_reset1, 185 isp_pci_dumpregs, 186 ISP_12160_RISC_CODE, 187 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 188 0 189 }; 190 #endif 191 192 #ifndef ISP_DISABLE_2100_SUPPORT 193 static struct ispmdvec mdvec_2100 = { 194 isp_pci_rd_isr, 195 isp_pci_rd_reg, 196 isp_pci_wr_reg, 197 isp_pci_mbxdma, 198 isp_pci_dmasetup, 199 isp_pci_dmateardown, 200 isp_pci_reset0, 201 isp_pci_reset1, 202 isp_pci_dumpregs, 203 ISP_2100_RISC_CODE, 204 0, 205 0 206 }; 207 #endif 208 209 #ifndef ISP_DISABLE_2200_SUPPORT 210 static struct ispmdvec mdvec_2200 = { 211 isp_pci_rd_isr, 212 isp_pci_rd_reg, 213 isp_pci_wr_reg, 214 isp_pci_mbxdma, 215 isp_pci_dmasetup, 216 isp_pci_dmateardown, 217 isp_pci_reset0, 218 isp_pci_reset1, 219 isp_pci_dumpregs, 220 ISP_2200_RISC_CODE, 221 0, 222 0 223 }; 224 #endif 225 226 #ifndef ISP_DISABLE_2300_SUPPORT 227 static struct ispmdvec mdvec_2300 = { 228 isp_pci_rd_isr_2300, 229 isp_pci_rd_reg, 230 isp_pci_wr_reg, 231 isp_pci_mbxdma, 232 isp_pci_dmasetup, 233 isp_pci_dmateardown, 234 isp_pci_reset0, 235 isp_pci_reset1, 236 isp_pci_dumpregs, 237 ISP_2300_RISC_CODE, 238 0, 239 0 240 }; 241 #endif 242 243 #ifndef ISP_DISABLE_2322_SUPPORT 244 static struct ispmdvec mdvec_2322 = { 245 isp_pci_rd_isr_2300, 246 isp_pci_rd_reg, 247 isp_pci_wr_reg, 248 isp_pci_mbxdma, 249 isp_pci_dmasetup, 250 isp_pci_dmateardown, 251 isp_pci_reset0, 252 isp_pci_reset1, 253 isp_pci_dumpregs, 254 ISP_2322_RISC_CODE, 255 0, 256 0 257 }; 258 #endif 259 260 #ifndef ISP_DISABLE_2400_SUPPORT 261 static struct ispmdvec mdvec_2400 = { 262 isp_pci_rd_isr_2400, 263 isp_pci_rd_reg_2400, 264 isp_pci_wr_reg_2400, 265 isp_pci_mbxdma, 266 isp_pci_dmasetup, 267 isp_pci_dmateardown, 268 isp_pci_reset0, 269 isp_pci_reset1, 270 NULL, 271 ISP_2400_RISC_CODE, 272 0, 273 0 274 }; 275 static struct ispmdvec mdvec_2500 = { 276 isp_pci_rd_isr_2400, 277 isp_pci_rd_reg_2400, 278 isp_pci_wr_reg_2400, 279 isp_pci_mbxdma, 280 isp_pci_dmasetup, 281 isp_pci_dmateardown, 282 isp_pci_reset0, 283 isp_pci_reset1, 284 NULL, 285 ISP_2500_RISC_CODE, 286 0, 287 0 288 }; 289 #endif 290 291 #ifndef PCI_VENDOR_QLOGIC 292 #define PCI_VENDOR_QLOGIC 0x1077 293 #endif 294 295 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 296 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 297 #endif 298 299 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 300 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 301 #endif 302 303 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 304 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 305 #endif 306 307 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 308 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 309 #endif 310 311 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 312 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 313 #endif 314 315 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 316 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 317 #endif 318 319 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 320 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 321 #endif 322 323 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 324 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 325 #endif 326 327 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 328 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 329 #endif 330 331 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 332 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 333 #endif 334 335 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 336 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 337 #endif 338 339 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 340 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 341 #endif 342 343 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 344 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 345 #endif 346 347 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 348 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 349 #endif 350 351 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 352 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 353 #endif 354 355 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 356 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 357 #endif 358 359 360 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 361 362 #define PCI_QLOGIC_ISP1080 \ 363 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 364 365 #define PCI_QLOGIC_ISP10160 \ 366 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 367 368 #define PCI_QLOGIC_ISP12160 \ 369 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 370 371 #define PCI_QLOGIC_ISP1240 \ 372 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 373 374 #define PCI_QLOGIC_ISP1280 \ 375 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 376 377 #define PCI_QLOGIC_ISP2100 \ 378 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 379 380 #define PCI_QLOGIC_ISP2200 \ 381 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 382 383 #define PCI_QLOGIC_ISP2300 \ 384 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 385 386 #define PCI_QLOGIC_ISP2312 \ 387 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 388 389 #define PCI_QLOGIC_ISP2322 \ 390 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 391 392 #define PCI_QLOGIC_ISP2422 \ 393 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 394 395 #define PCI_QLOGIC_ISP2432 \ 396 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 397 398 #define PCI_QLOGIC_ISP2532 \ 399 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 400 401 #define PCI_QLOGIC_ISP6312 \ 402 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 403 404 #define PCI_QLOGIC_ISP6322 \ 405 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 406 407 #define IO_MAP_REG 0x10 408 #define MEM_MAP_REG 0x14 409 #define PCIR_ROMADDR 0x30 410 411 #define PCI_DFLT_LTNCY 0x40 412 #define PCI_DFLT_LNSZ 0x10 413 414 static int isp_pci_probe(device_t, cfdata_t, void *); 415 static void isp_pci_attach(device_t, device_t, void *); 416 417 struct isp_pcisoftc { 418 struct ispsoftc pci_isp; 419 pci_chipset_tag_t pci_pc; 420 pcitag_t pci_tag; 421 bus_space_tag_t pci_st; 422 bus_space_handle_t pci_sh; 423 bus_dmamap_t *pci_xfer_dmap; 424 void * pci_ih; 425 int16_t pci_poff[_NREG_BLKS]; 426 }; 427 428 CFATTACH_DECL_NEW(isp_pci, sizeof (struct isp_pcisoftc), 429 isp_pci_probe, isp_pci_attach, NULL, NULL); 430 431 static int 432 isp_pci_probe(device_t parent, cfdata_t match, void *aux) 433 { 434 struct pci_attach_args *pa = aux; 435 switch (pa->pa_id) { 436 #ifndef ISP_DISABLE_1020_SUPPORT 437 case PCI_QLOGIC_ISP: 438 return (1); 439 #endif 440 #ifndef ISP_DISABLE_1080_SUPPORT 441 case PCI_QLOGIC_ISP1080: 442 case PCI_QLOGIC_ISP1240: 443 case PCI_QLOGIC_ISP1280: 444 return (1); 445 #endif 446 #ifndef ISP_DISABLE_12160_SUPPORT 447 case PCI_QLOGIC_ISP10160: 448 case PCI_QLOGIC_ISP12160: 449 return (1); 450 #endif 451 #ifndef ISP_DISABLE_2100_SUPPORT 452 case PCI_QLOGIC_ISP2100: 453 return (1); 454 #endif 455 #ifndef ISP_DISABLE_2200_SUPPORT 456 case PCI_QLOGIC_ISP2200: 457 return (1); 458 #endif 459 #ifndef ISP_DISABLE_2300_SUPPORT 460 case PCI_QLOGIC_ISP2300: 461 case PCI_QLOGIC_ISP2312: 462 case PCI_QLOGIC_ISP6312: 463 #endif 464 #ifndef ISP_DISABLE_2322_SUPPORT 465 case PCI_QLOGIC_ISP2322: 466 case PCI_QLOGIC_ISP6322: 467 return (1); 468 #endif 469 #ifndef ISP_DISABLE_2400_SUPPORT 470 case PCI_QLOGIC_ISP2422: 471 case PCI_QLOGIC_ISP2432: 472 case PCI_QLOGIC_ISP2532: 473 return (1); 474 #endif 475 default: 476 return (0); 477 } 478 } 479 480 static void 481 isp_pci_attach(device_t parent, device_t self, void *aux) 482 { 483 uint32_t data, rev, linesz = PCI_DFLT_LNSZ; 484 struct pci_attach_args *pa = aux; 485 struct isp_pcisoftc *pcs = device_private(self); 486 struct ispsoftc *isp = &pcs->pci_isp; 487 bus_space_tag_t st, iot, memt; 488 bus_space_handle_t sh, ioh, memh; 489 pci_intr_handle_t ih; 490 pcireg_t mem_type; 491 const char *dstring; 492 const char *intrstr; 493 int ioh_valid, memh_valid; 494 size_t mamt; 495 char intrbuf[PCI_INTRSTR_LEN]; 496 497 isp->isp_osinfo.dev = self; 498 499 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 500 &iot, &ioh, NULL, NULL) == 0); 501 502 mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MEM_MAP_REG); 503 if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) { 504 memh_valid = 0; 505 } else if (PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_32BIT && 506 PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_64BIT) { 507 memh_valid = 0; 508 } else { 509 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, mem_type, 0, 510 &memt, &memh, NULL, NULL) == 0); 511 } 512 if (memh_valid) { 513 st = memt; 514 sh = memh; 515 } else if (ioh_valid) { 516 st = iot; 517 sh = ioh; 518 } else { 519 aprint_error(": unable to map device registers\n"); 520 return; 521 } 522 dstring = "\n"; 523 524 isp->isp_nchan = 1; 525 mamt = 0; 526 527 pcs->pci_st = st; 528 pcs->pci_sh = sh; 529 pcs->pci_pc = pa->pa_pc; 530 pcs->pci_tag = pa->pa_tag; 531 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 532 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 533 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 534 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 535 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 536 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 537 538 539 #ifndef ISP_DISABLE_1020_SUPPORT 540 if (pa->pa_id == PCI_QLOGIC_ISP) { 541 dstring = ": QLogic 1020 Fast Wide SCSI HBA\n"; 542 isp->isp_mdvec = &mdvec; 543 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 544 mamt = sizeof (sdparam); 545 } 546 #endif 547 #ifndef ISP_DISABLE_1080_SUPPORT 548 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 549 dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n"; 550 isp->isp_mdvec = &mdvec_1080; 551 isp->isp_type = ISP_HA_SCSI_1080; 552 mamt = sizeof (sdparam); 553 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 554 ISP1080_DMA_REGS_OFF; 555 } 556 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 557 dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n"; 558 isp->isp_mdvec = &mdvec_1080; 559 isp->isp_type = ISP_HA_SCSI_1240; 560 isp->isp_nchan++; 561 mamt = sizeof (sdparam) * 2; 562 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 563 ISP1080_DMA_REGS_OFF; 564 } 565 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 566 dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n"; 567 isp->isp_mdvec = &mdvec_1080; 568 isp->isp_type = ISP_HA_SCSI_1280; 569 isp->isp_nchan++; 570 mamt = sizeof (sdparam) * 2; 571 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 572 ISP1080_DMA_REGS_OFF; 573 } 574 #endif 575 #ifndef ISP_DISABLE_12160_SUPPORT 576 if (pa->pa_id == PCI_QLOGIC_ISP10160) { 577 dstring = ": QLogic Ultra-3 Wide SCSI HBA\n"; 578 isp->isp_mdvec = &mdvec_12160; 579 isp->isp_type = ISP_HA_SCSI_10160; 580 mamt = sizeof (sdparam); 581 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 582 ISP1080_DMA_REGS_OFF; 583 } 584 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 585 dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n"; 586 isp->isp_mdvec = &mdvec_12160; 587 isp->isp_type = ISP_HA_SCSI_12160; 588 isp->isp_nchan++; 589 mamt = sizeof (sdparam) * 2; 590 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 591 ISP1080_DMA_REGS_OFF; 592 } 593 #endif 594 #ifndef ISP_DISABLE_2100_SUPPORT 595 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 596 dstring = ": QLogic FC-AL HBA\n"; 597 isp->isp_mdvec = &mdvec_2100; 598 isp->isp_type = ISP_HA_FC_2100; 599 mamt = sizeof (fcparam); 600 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 601 PCI_MBOX_REGS2100_OFF; 602 if (rev < 3) { 603 /* 604 * XXX: Need to get the actual revision 605 * XXX: number of the 2100 FB. At any rate, 606 * XXX: lower cache line size for early revision 607 * XXX; boards. 608 */ 609 linesz = 1; 610 } 611 } 612 #endif 613 #ifndef ISP_DISABLE_2200_SUPPORT 614 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 615 dstring = ": QLogic FC-AL and Fabric HBA\n"; 616 isp->isp_mdvec = &mdvec_2200; 617 isp->isp_type = ISP_HA_FC_2200; 618 mamt = sizeof (fcparam); 619 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 620 PCI_MBOX_REGS2100_OFF; 621 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 622 } 623 #endif 624 #ifndef ISP_DISABLE_2300_SUPPORT 625 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 626 pa->pa_id == PCI_QLOGIC_ISP2312 || 627 pa->pa_id == PCI_QLOGIC_ISP6312) { 628 isp->isp_mdvec = &mdvec_2300; 629 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 630 pa->pa_id == PCI_QLOGIC_ISP6312) { 631 dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n"; 632 isp->isp_type = ISP_HA_FC_2300; 633 } else { 634 dstring = 635 ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n"; 636 isp->isp_port = pa->pa_function; 637 } 638 isp->isp_type = ISP_HA_FC_2312; 639 mamt = sizeof (fcparam); 640 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 641 PCI_MBOX_REGS2300_OFF; 642 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 643 } 644 #endif 645 #ifndef ISP_DISABLE_2322_SUPPORT 646 if (pa->pa_id == PCI_QLOGIC_ISP2322 || 647 pa->pa_id == PCI_QLOGIC_ISP6322) { 648 isp->isp_mdvec = &mdvec_2322; 649 dstring = ": QLogic FC-AL and 2Gbps Fabric PCI-E HBA\n"; 650 isp->isp_type = ISP_HA_FC_2322; 651 isp->isp_port = pa->pa_function; 652 mamt = sizeof (fcparam); 653 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 654 PCI_MBOX_REGS2300_OFF; 655 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 656 } 657 #endif 658 #ifndef ISP_DISABLE_2400_SUPPORT 659 if (pa->pa_id == PCI_QLOGIC_ISP2422 || 660 pa->pa_id == PCI_QLOGIC_ISP2432) { 661 isp->isp_mdvec = &mdvec_2400; 662 if (pa->pa_id == PCI_QLOGIC_ISP2422) { 663 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-X HBA\n"; 664 } else { 665 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-E HBA\n"; 666 } 667 isp->isp_type = ISP_HA_FC_2400; 668 isp->isp_port = pa->pa_function; 669 mamt = sizeof (fcparam); 670 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 671 PCI_MBOX_REGS2400_OFF; 672 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 673 } 674 if (pa->pa_id == PCI_QLOGIC_ISP2532) { 675 isp->isp_mdvec = &mdvec_2500; 676 dstring = ": QLogic FC-AL and 8Gbps Fabric PCI-E HBA\n"; 677 isp->isp_type = ISP_HA_FC_2500; 678 isp->isp_port = pa->pa_function; 679 mamt = sizeof (fcparam); 680 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 681 PCI_MBOX_REGS2400_OFF; 682 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 683 } 684 #endif 685 if (mamt == 0) { 686 return; 687 } 688 689 isp->isp_param = malloc(mamt, M_DEVBUF, M_WAITOK | M_ZERO); 690 mamt = sizeof (struct scsipi_channel) * isp->isp_nchan; 691 isp->isp_osinfo.chan = malloc(mamt, M_DEVBUF, M_WAITOK | M_ZERO); 692 isp->isp_osinfo.adapter.adapt_nchannels = isp->isp_nchan; 693 694 /* 695 * Set up logging levels. 696 */ 697 #ifdef ISP_LOGDEFAULT 698 isp->isp_dblev = ISP_LOGDEFAULT; 699 #else 700 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 701 if (bootverbose) 702 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 703 #ifdef SCSIDEBUG 704 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2; 705 #endif 706 #endif 707 if (isp->isp_dblev & ISP_LOGCONFIG) { 708 aprint_normal("\n"); 709 } else { 710 aprint_normal("%s", dstring); 711 } 712 713 /* 714 * XXX isp_intr() seems to have some logic error 715 * XXX with respect to RQSTYPE_A64, so just avoid 716 * XXX it for now. 717 */ 718 #if 0 719 if (pci_dma64_available(pa)) { 720 isp->isp_dmatag = pa->pa_dmat64; 721 isp->isp_use_dma64 = 1; 722 } else 723 #endif 724 isp->isp_dmatag = pa->pa_dmat; 725 isp->isp_revision = rev; 726 727 /* 728 * Make sure that command register set sanely. 729 */ 730 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 731 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 732 733 /* 734 * Not so sure about these- but I think it's important that they get 735 * enabled...... 736 */ 737 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 738 if (IS_2300(isp)) { /* per QLogic errata */ 739 data &= ~PCI_COMMAND_INVALIDATE_ENABLE; 740 } 741 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 742 743 /* 744 * Make sure that the latency timer, cache line size, 745 * and ROM is disabled. 746 */ 747 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 748 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 749 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 750 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 751 data |= (linesz << PCI_CACHELINE_SHIFT); 752 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 753 754 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 755 data &= ~1; 756 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 757 758 if (pci_intr_map(pa, &ih)) { 759 aprint_error_dev(self, "couldn't map interrupt\n"); 760 free(isp->isp_param, M_DEVBUF); 761 free(isp->isp_osinfo.chan, M_DEVBUF); 762 return; 763 } 764 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 765 if (intrstr == NULL) 766 intrstr = "<I dunno>"; 767 pcs->pci_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_BIO, 768 isp_pci_intr, isp, device_xname(self)); 769 if (pcs->pci_ih == NULL) { 770 aprint_error_dev(self, "couldn't establish interrupt at %s\n", 771 intrstr); 772 free(isp->isp_param, M_DEVBUF); 773 free(isp->isp_osinfo.chan, M_DEVBUF); 774 return; 775 } 776 777 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 778 779 isp->isp_confopts = device_cfdata(self)->cf_flags; 780 ISP_LOCK(isp); 781 isp_reset(isp, 1); 782 if (isp->isp_state != ISP_RESETSTATE) { 783 ISP_UNLOCK(isp); 784 free(isp->isp_param, M_DEVBUF); 785 free(isp->isp_osinfo.chan, M_DEVBUF); 786 return; 787 } 788 isp_init(isp); 789 if (isp->isp_state != ISP_INITSTATE) { 790 isp_uninit(isp); 791 ISP_UNLOCK(isp); 792 free(isp->isp_param, M_DEVBUF); 793 free(isp->isp_osinfo.chan, M_DEVBUF); 794 return; 795 } 796 /* 797 * Do platform attach. 798 */ 799 ISP_UNLOCK(isp); 800 isp_attach(isp); 801 } 802 803 #define IspVirt2Off(a, x) \ 804 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 805 _BLK_REG_SHFT] + ((x) & 0xff)) 806 807 #define BXR2(pcs, off) \ 808 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 809 #define BXW2(pcs, off, v) \ 810 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 811 #define BXR4(pcs, off) \ 812 bus_space_read_4(pcs->pci_st, pcs->pci_sh, off) 813 #define BXW4(pcs, off, v) \ 814 bus_space_write_4(pcs->pci_st, pcs->pci_sh, off, v) 815 816 817 static int 818 isp_pci_rd_debounced(struct ispsoftc *isp, int off, uint16_t *rp) 819 { 820 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 821 uint16_t val0, val1; 822 int i = 0; 823 824 do { 825 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 826 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 827 } while (val0 != val1 && ++i < 1000); 828 if (val0 != val1) { 829 return (1); 830 } 831 *rp = val0; 832 return (0); 833 } 834 835 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 836 !defined(ISP_DISABLE_2200_SUPPORT) && \ 837 !defined(ISP_DISABLE_1020_SUPPORT) && \ 838 !defined(ISP_DISABLE_1080_SUPPORT) && \ 839 !defined(ISP_DISABLE_12160_SUPPORT) 840 static int 841 isp_pci_rd_isr(struct ispsoftc *isp, uint32_t *isrp, 842 uint16_t *semap, uint16_t *mbp) 843 { 844 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 845 uint16_t isr, sema; 846 847 if (IS_2100(isp)) { 848 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 849 return (0); 850 } 851 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 852 return (0); 853 } 854 } else { 855 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 856 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 857 } 858 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 859 isr &= INT_PENDING_MASK(isp); 860 sema &= BIU_SEMA_LOCK; 861 if (isr == 0 && sema == 0) { 862 return (0); 863 } 864 *isrp = isr; 865 if ((*semap = sema) != 0) { 866 if (IS_2100(isp)) { 867 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 868 return (0); 869 } 870 } else { 871 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 872 } 873 } 874 return (1); 875 } 876 #endif 877 878 #if !(defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_2322_SUPPORT)) 879 static int 880 isp_pci_rd_isr_2300(struct ispsoftc *isp, uint32_t *isrp, 881 uint16_t *semap, uint16_t *mbox0p) 882 { 883 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 884 uint32_t r2hisr; 885 886 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { 887 *isrp = 0; 888 return (0); 889 } 890 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 891 IspVirt2Off(pcs, BIU_R2HSTSLO)); 892 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 893 if ((r2hisr & BIU_R2HST_INTR) == 0) { 894 *isrp = 0; 895 return (0); 896 } 897 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 898 case ISPR2HST_ROM_MBX_OK: 899 case ISPR2HST_ROM_MBX_FAIL: 900 case ISPR2HST_MBX_OK: 901 case ISPR2HST_MBX_FAIL: 902 case ISPR2HST_ASYNC_EVENT: 903 *isrp = r2hisr & 0xffff; 904 *mbox0p = (r2hisr >> 16); 905 *semap = 1; 906 return (1); 907 case ISPR2HST_RIO_16: 908 *isrp = r2hisr & 0xffff; 909 *mbox0p = ASYNC_RIO16_1; 910 *semap = 1; 911 return (1); 912 case ISPR2HST_FPOST: 913 *isrp = r2hisr & 0xffff; 914 *mbox0p = ASYNC_CMD_CMPLT; 915 *semap = 1; 916 return (1); 917 case ISPR2HST_FPOST_CTIO: 918 *isrp = r2hisr & 0xffff; 919 *mbox0p = ASYNC_CTIO_DONE; 920 *semap = 1; 921 return (1); 922 case ISPR2HST_RSPQ_UPDATE: 923 *isrp = r2hisr & 0xffff; 924 *mbox0p = 0; 925 *semap = 0; 926 return (1); 927 default: 928 return (0); 929 } 930 } 931 #endif 932 933 #ifndef ISP_DISABLE_2400_SUPPORT 934 static int 935 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, 936 uint16_t *semap, uint16_t *mbox0p) 937 { 938 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 939 uint32_t r2hisr; 940 941 r2hisr = BXR4(pcs, IspVirt2Off(pcs, BIU2400_R2HSTSLO)); 942 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 943 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 944 *isrp = 0; 945 return (0); 946 } 947 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 948 case ISP2400R2HST_ROM_MBX_OK: 949 case ISP2400R2HST_ROM_MBX_FAIL: 950 case ISP2400R2HST_MBX_OK: 951 case ISP2400R2HST_MBX_FAIL: 952 case ISP2400R2HST_ASYNC_EVENT: 953 *isrp = r2hisr & 0xffff; 954 *mbox0p = (r2hisr >> 16); 955 *semap = 1; 956 return (1); 957 case ISP2400R2HST_RSPQ_UPDATE: 958 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 959 case ISP2400R2HST_ATIO_RQST_UPDATE: 960 *isrp = r2hisr & 0xffff; 961 *mbox0p = 0; 962 *semap = 0; 963 return (1); 964 default: 965 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 966 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 967 return (0); 968 } 969 } 970 971 static uint32_t 972 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 973 { 974 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 975 uint32_t rv; 976 int block = regoff & _BLK_REG_MASK; 977 978 switch (block) { 979 case BIU_BLOCK: 980 break; 981 case MBOX_BLOCK: 982 return (BXR2(pcs, IspVirt2Off(pcs, regoff))); 983 case SXP_BLOCK: 984 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 985 return (0xffffffff); 986 case RISC_BLOCK: 987 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 988 return (0xffffffff); 989 case DMA_BLOCK: 990 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 991 return (0xffffffff); 992 default: 993 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 994 return (0xffffffff); 995 } 996 997 998 switch (regoff) { 999 case BIU2400_FLASH_ADDR: 1000 case BIU2400_FLASH_DATA: 1001 case BIU2400_ICR: 1002 case BIU2400_ISR: 1003 case BIU2400_CSR: 1004 case BIU2400_REQINP: 1005 case BIU2400_REQOUTP: 1006 case BIU2400_RSPINP: 1007 case BIU2400_RSPOUTP: 1008 case BIU2400_PRI_REQINP: 1009 case BIU2400_PRI_REQOUTP: 1010 case BIU2400_ATIO_RSPINP: 1011 case BIU2400_ATIO_RSPOUTP: 1012 case BIU2400_HCCR: 1013 case BIU2400_GPIOD: 1014 case BIU2400_GPIOE: 1015 case BIU2400_HSEMA: 1016 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1017 break; 1018 case BIU2400_R2HSTSLO: 1019 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1020 break; 1021 case BIU2400_R2HSTSHI: 1022 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)) >> 16; 1023 break; 1024 default: 1025 isp_prt(isp, ISP_LOGERR, 1026 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1027 rv = 0xffffffff; 1028 break; 1029 } 1030 return (rv); 1031 } 1032 1033 static void 1034 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1035 { 1036 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1037 int block = regoff & _BLK_REG_MASK; 1038 1039 switch (block) { 1040 case BIU_BLOCK: 1041 break; 1042 case MBOX_BLOCK: 1043 BXW2(pcs, IspVirt2Off(pcs, regoff), val); 1044 (void)BXR2(pcs, IspVirt2Off(pcs, regoff)); 1045 return; 1046 case SXP_BLOCK: 1047 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1048 return; 1049 case RISC_BLOCK: 1050 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1051 return; 1052 case DMA_BLOCK: 1053 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1054 return; 1055 default: 1056 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1057 regoff); 1058 break; 1059 } 1060 1061 switch (regoff) { 1062 case BIU2400_FLASH_ADDR: 1063 case BIU2400_FLASH_DATA: 1064 case BIU2400_ICR: 1065 case BIU2400_ISR: 1066 case BIU2400_CSR: 1067 case BIU2400_REQINP: 1068 case BIU2400_REQOUTP: 1069 case BIU2400_RSPINP: 1070 case BIU2400_RSPOUTP: 1071 case BIU2400_PRI_REQINP: 1072 case BIU2400_PRI_REQOUTP: 1073 case BIU2400_ATIO_RSPINP: 1074 case BIU2400_ATIO_RSPOUTP: 1075 case BIU2400_HCCR: 1076 case BIU2400_GPIOD: 1077 case BIU2400_GPIOE: 1078 case BIU2400_HSEMA: 1079 BXW4(pcs, IspVirt2Off(pcs, regoff), val); 1080 (void)BXR4(pcs, IspVirt2Off(pcs, regoff)); 1081 break; 1082 default: 1083 isp_prt(isp, ISP_LOGERR, 1084 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1085 break; 1086 } 1087 } 1088 #endif 1089 1090 static uint32_t 1091 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 1092 { 1093 uint32_t rv; 1094 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1095 int oldconf = 0; 1096 1097 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1098 /* 1099 * We will assume that someone has paused the RISC processor. 1100 */ 1101 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1102 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1103 oldconf | BIU_PCI_CONF1_SXP); 1104 } 1105 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1106 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1107 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 1108 } 1109 return (rv); 1110 } 1111 1112 static void 1113 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, uint32_t val) 1114 { 1115 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1116 int oldconf = 0; 1117 1118 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1119 /* 1120 * We will assume that someone has paused the RISC processor. 1121 */ 1122 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1123 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1124 oldconf | BIU_PCI_CONF1_SXP); 1125 } 1126 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1127 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1128 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 1129 } 1130 } 1131 1132 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 1133 static uint32_t 1134 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 1135 { 1136 uint16_t rv, oc = 0; 1137 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1138 1139 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1140 uint16_t tc; 1141 /* 1142 * We will assume that someone has paused the RISC processor. 1143 */ 1144 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1145 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1146 if (regoff & SXP_BANK1_SELECT) 1147 tc |= BIU_PCI1080_CONF1_SXP1; 1148 else 1149 tc |= BIU_PCI1080_CONF1_SXP0; 1150 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1151 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1152 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1153 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1154 oc | BIU_PCI1080_CONF1_DMA); 1155 } 1156 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1157 if (oc) { 1158 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1159 } 1160 return (rv); 1161 } 1162 1163 static void 1164 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, uint32_t val) 1165 { 1166 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1167 int oc = 0; 1168 1169 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1170 uint16_t tc; 1171 /* 1172 * We will assume that someone has paused the RISC processor. 1173 */ 1174 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1175 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1176 if (regoff & SXP_BANK1_SELECT) 1177 tc |= BIU_PCI1080_CONF1_SXP1; 1178 else 1179 tc |= BIU_PCI1080_CONF1_SXP0; 1180 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1181 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1182 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1183 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1184 oc | BIU_PCI1080_CONF1_DMA); 1185 } 1186 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1187 if (oc) { 1188 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1189 } 1190 } 1191 #endif 1192 1193 static int 1194 isp_pci_mbxdma(struct ispsoftc *isp) 1195 { 1196 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1197 bus_dma_tag_t dmat = isp->isp_dmatag; 1198 bus_dma_segment_t sg; 1199 bus_size_t len, dbound; 1200 fcparam *fcp; 1201 int rs, i; 1202 1203 if (isp->isp_rquest_dma) /* been here before? */ 1204 return (0); 1205 1206 if (isp->isp_type <= ISP_HA_SCSI_1040B) { 1207 dbound = 1 << 24; 1208 } else { 1209 /* 1210 * For 32-bit PCI DMA, the range is 32 bits or zero :-) 1211 */ 1212 dbound = 0; 1213 } 1214 len = isp->isp_maxcmds * sizeof (isp_hdl_t); 1215 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK); 1216 if (isp->isp_xflist == NULL) { 1217 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 1218 return (1); 1219 } 1220 memset(isp->isp_xflist, 0, len); 1221 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1222 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1223 } 1224 isp->isp_xffree = isp->isp_xflist; 1225 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 1226 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1227 if (pcs->pci_xfer_dmap == NULL) { 1228 free(isp->isp_xflist, M_DEVBUF); 1229 isp->isp_xflist = NULL; 1230 isp_prt(isp, ISP_LOGERR, "cannot malloc DMA map array"); 1231 return (1); 1232 } 1233 for (i = 0; i < isp->isp_maxcmds; i++) { 1234 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 1235 MAXPHYS, dbound, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 1236 isp_prt(isp, ISP_LOGERR, "cannot create DMA maps"); 1237 break; 1238 } 1239 } 1240 if (i < isp->isp_maxcmds) { 1241 while (--i >= 0) { 1242 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1243 } 1244 free(isp->isp_xflist, M_DEVBUF); 1245 free(pcs->pci_xfer_dmap, M_DEVBUF); 1246 isp->isp_xflist = NULL; 1247 pcs->pci_xfer_dmap = NULL; 1248 return (1); 1249 } 1250 1251 /* 1252 * Allocate and map the request queue. 1253 */ 1254 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1255 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 0)) { 1256 goto dmafail; 1257 } 1258 if (bus_dmamem_map(isp->isp_dmatag, &sg, rs, len, 1259 (void *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1260 goto dmafail; 1261 } 1262 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT, 1263 &isp->isp_rqdmap)) { 1264 goto dmafail; 1265 } 1266 if (bus_dmamap_load(dmat, isp->isp_rqdmap, isp->isp_rquest, len, NULL, 1267 BUS_DMA_NOWAIT)) { 1268 goto dmafail; 1269 } 1270 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr; 1271 1272 /* 1273 * Allocate and map the result queue. 1274 */ 1275 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1276 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 1277 BUS_DMA_NOWAIT)) { 1278 goto dmafail; 1279 } 1280 if (bus_dmamem_map(dmat, &sg, rs, len, 1281 (void *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1282 goto dmafail; 1283 } 1284 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT, 1285 &isp->isp_rsdmap)) { 1286 goto dmafail; 1287 } 1288 if (bus_dmamap_load(dmat, isp->isp_rsdmap, isp->isp_result, len, NULL, 1289 BUS_DMA_NOWAIT)) { 1290 goto dmafail; 1291 } 1292 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr; 1293 1294 if (IS_SCSI(isp)) { 1295 return (0); 1296 } 1297 1298 /* 1299 * Allocate and map an FC scratch area 1300 */ 1301 fcp = isp->isp_param; 1302 len = ISP_FC_SCRLEN; 1303 if (bus_dmamem_alloc(dmat, len, sizeof (uint64_t), 0, &sg, 1, &rs, 1304 BUS_DMA_NOWAIT)) { 1305 goto dmafail; 1306 } 1307 if (bus_dmamem_map(dmat, &sg, rs, len, 1308 (void *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1309 goto dmafail; 1310 } 1311 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT, 1312 &isp->isp_scdmap)) { 1313 goto dmafail; 1314 } 1315 if (bus_dmamap_load(dmat, isp->isp_scdmap, fcp->isp_scratch, len, NULL, 1316 BUS_DMA_NOWAIT)) { 1317 goto dmafail; 1318 } 1319 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr; 1320 return (0); 1321 dmafail: 1322 isp_prt(isp, ISP_LOGERR, "mailbox DMA setup failure"); 1323 for (i = 0; i < isp->isp_maxcmds; i++) { 1324 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1325 } 1326 free(isp->isp_xflist, M_DEVBUF); 1327 free(pcs->pci_xfer_dmap, M_DEVBUF); 1328 isp->isp_xflist = NULL; 1329 pcs->pci_xfer_dmap = NULL; 1330 return (1); 1331 } 1332 1333 static int 1334 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, void *arg) 1335 { 1336 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1337 ispreq_t *rq = arg; 1338 bus_dmamap_t dmap; 1339 bus_dma_segment_t *dm_segs; 1340 uint32_t nsegs, hidx; 1341 isp_ddir_t ddir; 1342 1343 hidx = isp_handle_index(isp, rq->req_handle); 1344 if (hidx == ISP_BAD_HANDLE_INDEX) { 1345 XS_SETERR(xs, HBA_BOTCH); 1346 return (CMD_COMPLETE); 1347 } 1348 dmap = pcs->pci_xfer_dmap[hidx]; 1349 if (xs->datalen == 0) { 1350 ddir = ISP_NOXFR; 1351 nsegs = 0; 1352 dm_segs = NULL; 1353 } else { 1354 int error; 1355 uint32_t flag, flg2; 1356 1357 if (isp->isp_use_dma64) { 1358 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1359 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1360 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1361 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1362 } 1363 } 1364 1365 if (xs->xs_control & XS_CTL_DATA_IN) { 1366 flg2 = BUS_DMASYNC_PREREAD; 1367 flag = BUS_DMA_READ; 1368 ddir = ISP_FROM_DEVICE; 1369 } else { 1370 flg2 = BUS_DMASYNC_PREWRITE; 1371 flag = BUS_DMA_WRITE; 1372 ddir = ISP_TO_DEVICE; 1373 } 1374 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, 1375 xs->datalen, NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 1376 BUS_DMA_NOWAIT : 1377 BUS_DMA_WAITOK) | BUS_DMA_STREAMING | flag); 1378 if (error) { 1379 isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)", 1380 error); 1381 XS_SETERR(xs, HBA_BOTCH); 1382 if (error == EAGAIN || error == ENOMEM) { 1383 return (CMD_EAGAIN); 1384 } else { 1385 return (CMD_COMPLETE); 1386 } 1387 } 1388 dm_segs = dmap->dm_segs; 1389 nsegs = dmap->dm_nsegs; 1390 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1391 flg2); 1392 } 1393 1394 if (isp_send_cmd(isp, rq, dm_segs, nsegs, xs->datalen, ddir) 1395 != CMD_QUEUED) { 1396 return (CMD_EAGAIN); 1397 } else { 1398 return (CMD_QUEUED); 1399 } 1400 } 1401 1402 static int 1403 isp_pci_intr(void *arg) 1404 { 1405 uint32_t isr; 1406 uint16_t sema, mbox; 1407 struct ispsoftc *isp = arg; 1408 1409 isp->isp_intcnt++; 1410 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1411 isp->isp_intbogus++; 1412 return (0); 1413 } else { 1414 isp->isp_osinfo.onintstack = 1; 1415 isp_intr(isp, isr, sema, mbox); 1416 isp->isp_osinfo.onintstack = 0; 1417 return (1); 1418 } 1419 } 1420 1421 static void 1422 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, uint32_t handle) 1423 { 1424 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1425 uint32_t hidx; 1426 bus_dmamap_t dmap; 1427 1428 hidx = isp_handle_index(isp, handle); 1429 if (hidx == ISP_BAD_HANDLE_INDEX) { 1430 isp_xs_prt(isp, xs, ISP_LOGERR, "bad handle on teardown"); 1431 return; 1432 } 1433 dmap = pcs->pci_xfer_dmap[hidx]; 1434 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1435 xs->xs_control & XS_CTL_DATA_IN ? 1436 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1437 bus_dmamap_unload(isp->isp_dmatag, dmap); 1438 } 1439 1440 static void 1441 isp_pci_reset0(ispsoftc_t *isp) 1442 { 1443 ISP_DISABLE_INTS(isp); 1444 } 1445 1446 static void 1447 isp_pci_reset1(ispsoftc_t *isp) 1448 { 1449 if (!IS_24XX(isp)) { 1450 /* Make sure the BIOS is disabled */ 1451 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1452 } 1453 /* and enable interrupts */ 1454 ISP_ENABLE_INTS(isp); 1455 } 1456 1457 static void 1458 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1459 { 1460 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1461 if (msg) 1462 printf("%s: %s\n", device_xname(isp->isp_osinfo.dev), msg); 1463 if (IS_SCSI(isp)) 1464 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1465 else 1466 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1467 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1468 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1469 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1470 1471 1472 if (IS_SCSI(isp)) { 1473 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1474 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1475 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1476 ISP_READ(isp, CDMA_FIFO_STS)); 1477 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1478 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1479 ISP_READ(isp, DDMA_FIFO_STS)); 1480 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1481 ISP_READ(isp, SXP_INTERRUPT), 1482 ISP_READ(isp, SXP_GROSS_ERR), 1483 ISP_READ(isp, SXP_PINS_CTRL)); 1484 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1485 } 1486 printf(" mbox regs: %x %x %x %x %x\n", 1487 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1488 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1489 ISP_READ(isp, OUTMAILBOX4)); 1490 printf(" PCI Status Command/Status=%x\n", 1491 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1492 } 1493
Indexes created Sun Oct 25 00:26:45 UTC 2026