| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| aarch64-sim.h | 38 uint32_t FPCR; /* Floating point Control register. */
|
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| aarch64-sim.h | 38 uint32_t FPCR; /* Floating point Control register. */
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| m10300-opc.c | 345 #define FPCR (SIMM4_6+1)
365 #define FSM0 (FPCR+1)
1048 { "fmov", 0xf9b500, 0xffff0f, 0, FMT_D6, AM33_2, {RM2, FPCR}},
1049 { "fmov", 0xf9b700, 0xfffff0, 0, FMT_D6, AM33_2, {FPCR, RM0}},
1082 { "fmov", 0xfdb50000, 0xffff0000, 0, FMT_D4, AM33_2, {IMM32, FPCR}},
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| m10300-opc.c | 345 #define FPCR (SIMM4_6+1)
365 #define FSM0 (FPCR+1)
1048 { "fmov", 0xf9b500, 0xffff0f, 0, FMT_D6, AM33_2, {RM2, FPCR}},
1049 { "fmov", 0xf9b700, 0xfffff0, 0, FMT_D6, AM33_2, {FPCR, RM0}},
1082 { "fmov", 0xfdb50000, 0xffff0000, 0, FMT_D4, AM33_2, {IMM32, FPCR}},
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| m10300-opc.c | 345 #define FPCR (SIMM4_6+1)
365 #define FSM0 (FPCR+1)
1048 { "fmov", 0xf9b500, 0xffff0f, 0, FMT_D6, AM33_2, {RM2, FPCR}},
1049 { "fmov", 0xf9b700, 0xfffff0, 0, FMT_D6, AM33_2, {FPCR, RM0}},
1082 { "fmov", 0xfdb50000, 0xffff0000, 0, FMT_D4, AM33_2, {IMM32, FPCR}},
|
| /src/external/gpl3/gdb/dist/sim/mn10300/ |
| mn10300-sim.h | 84 #define FPCR (State.regs[REG_FPCR])
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| m10300-opc.c | 345 #define FPCR (SIMM4_6+1)
365 #define FSM0 (FPCR+1)
1048 { "fmov", 0xf9b500, 0xffff0f, 0, FMT_D6, AM33_2, {RM2, FPCR}},
1049 { "fmov", 0xf9b700, 0xfffff0, 0, FMT_D6, AM33_2, {FPCR, RM0}},
1082 { "fmov", 0xfdb50000, 0xffff0000, 0, FMT_D4, AM33_2, {IMM32, FPCR}},
|
| /src/external/gpl3/gdb.old/dist/sim/mn10300/ |
| mn10300-sim.h | 84 #define FPCR (State.regs[REG_FPCR])
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| m68k-parse.c | 181 FPCR = 261, /* FPCR */
200 #define FPCR 261
248 YYSYMBOL_FPCR = 6, /* FPCR */
701 "FPCR", "LPC", "ZAR", "ZDR", "LZPC", "CREG", "INDEXREG", "EXPR", "'&'",
1429 case 12: /* generic_operand: FPCR */
2056 case 89: /* reglistreg: FPCR */
2450 return FPCR;
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| m68k-parse.c | 181 FPCR = 261, /* FPCR */
200 #define FPCR 261
248 YYSYMBOL_FPCR = 6, /* FPCR */
701 "FPCR", "LPC", "ZAR", "ZDR", "LZPC", "CREG", "INDEXREG", "EXPR", "'&'",
1429 case 12: /* generic_operand: FPCR */
2056 case 89: /* reglistreg: FPCR */
2450 return FPCR;
|
| /src/external/gpl3/gdb/dist/gdbserver/ |
| linux-aarch64-low.cc | 234 collect_register (regcache, AARCH64_FPCR_REGNUM, ®set->fpcr);
247 supply_register (regcache, AARCH64_FPCR_REGNUM, ®set->fpcr);
1178 - FPCR: Floating-point control registers.
1186 FPCR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
2295 | FPCR | <- SP + 16
2361 /* Save CPSR (NZCV), FPSR and FPCR:
2365 MRS x0, fpcr
2374 p += emit_mrs (p, x0, FPCR);
2500 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2509 MSR FPCR, x
[all...] |
| /src/external/gpl3/gdb.old/dist/gdbserver/ |
| linux-aarch64-low.cc | 234 collect_register (regcache, AARCH64_FPCR_REGNUM, ®set->fpcr);
247 supply_register (regcache, AARCH64_FPCR_REGNUM, ®set->fpcr);
1182 - FPCR: Floating-point control registers.
1190 FPCR = (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
2299 | FPCR | <- SP + 16
2365 /* Save CPSR (NZCV), FPSR and FPCR:
2369 MRS x0, fpcr
2378 p += emit_mrs (p, x0, FPCR);
2504 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2513 MSR FPCR, x
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 3629 // The rounding mode is in bits 23:22 of the FPCR.
3630 // The llvm.set.rounding argument value to the rounding mode in FPCR mapping
3638 // Calculate new value of FPCR[23:22].
3648 // Get current value of FPCR.
3651 SDValue FPCR =
3653 Chain = FPCR.getValue(1);
3654 FPCR = FPCR.getValue(0);
3658 FPCR = DAG.getNode(ISD::AND, DL, MVT::i64, FPCR,
[all...] |
