1 /* $NetBSD: am18xx_psc.c,v 1.6 2026/08/12 09:22:08 yurix Exp $ */ 2 3 /*- 4 * Copyright (c) 2025 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Yuri Honegger. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Power&Sleep Controller for the TI AM18XX SOC. 34 * 35 * Locking Strategy: All hardware interactions, as well as 36 * am18xx_psc_clk.clk_refcount should be touched with sc->sc_lock held. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/cdefs.h> 41 #include <sys/device.h> 42 #include <sys/mutex.h> 43 44 #include <dev/clk/clk_backend.h> 45 #include <dev/fdt/fdtvar.h> 46 47 #include <arm/fdt/arm_fdtvar.h> 48 49 struct am18xx_psc_clk { 50 struct clk clk_base; /* must be first */ 51 int clk_index; 52 union { 53 const char *clk_parent_name; 54 struct clk *clk_parent; 55 } u; 56 /* Some clocks might be enabled by multiple consumers. Only disable it 57 * if no consumer is using it anymore. */ 58 uint clk_refcount; 59 }; 60 61 struct am18xx_psc_config { 62 struct am18xx_psc_clk *clks; 63 int clknum; 64 }; 65 66 struct am18xx_psc_softc { 67 bus_space_tag_t sc_bst; 68 bus_space_handle_t sc_bsh; 69 struct clk_domain sc_clkdom; 70 kmutex_t sc_lock; 71 struct am18xx_psc_clk *sc_clks; 72 int sc_clknum; 73 }; 74 75 static int am18xx_psc_match(device_t, cfdata_t, void *); 76 static void am18xx_psc_attach(device_t, device_t, void *); 77 static struct clk * am18xx_psc_decode(device_t, int, const void *, size_t); 78 static struct clk * am18xx_psc_clk_get(void *, const char *); 79 static u_int am18xx_psc_clk_get_rate(void *, struct clk *); 80 static int am18xx_psc_clk_enable(void *, struct clk *); 81 static int am18xx_psc_clk_disable(void *, struct clk *); 82 static struct clk * am18xx_psc_clk_get_parent(void *, struct clk *); 83 static void am18xx_psc_clk_transition(struct am18xx_psc_softc *, 84 struct am18xx_psc_clk *, 85 uint32_t); 86 static void am18xx_psc_powerdomain_enable(device_t, 87 const uint32_t *, 88 bool); 89 90 CFATTACH_DECL_NEW(am18xxpsc, sizeof(struct am18xx_psc_softc), 91 am18xx_psc_match, am18xx_psc_attach, NULL, NULL); 92 93 #define AM18XX_PSC_PTCMD 0x120 94 #define AM18XX_PSC_PTSTAT 0x128 95 #define AM18XX_PSC_MDCTL0 0xA00 96 97 #define AM18XX_PSC_PTCMD_GO_ALL 0x3 98 #define AM18XX_PSC_PTSTAT_MASK 0x3 99 #define AM18XX_PSC_MDCTL_DISABLE 0x2 100 #define AM18XX_PSC_MDCTL_ENABLE 0x3 101 102 #define PSC_READ(sc, reg) \ 103 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, reg) 104 #define PSC_WRITE(sc, reg, val) \ 105 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, reg, val) 106 107 #define PSC_CLK(_i, _name, _p) \ 108 { \ 109 .clk_index = (_i), \ 110 .u.clk_parent_name = (_p), \ 111 .clk_base.name = (_name), \ 112 .clk_base.flags = 0, \ 113 .clk_refcount = 0, \ 114 } 115 116 static struct am18xx_psc_clk am18xx_psc0_clks[] = { 117 PSC_CLK(0, "edma0_cc0", "pll0_sysclk2"), 118 PSC_CLK(1, "edma0_tc0", "pll0_sysclk2"), 119 PSC_CLK(2, "edma0_tc1", "pll0_sysclk2"), 120 PSC_CLK(3, "emifa", "async1"), 121 PSC_CLK(4, "spi0", "pll0_sysclk2"), 122 PSC_CLK(5, "sdmmc0", "pll0_sysclk2"), 123 PSC_CLK(6, "aintc", "pll0_sysclk4"), 124 PSC_CLK(7, "imem", "pll0_sysclk2"), 125 PSC_CLK(8, NULL, NULL), /* unused */ 126 PSC_CLK(9, "uart0", "pll0_sysclk2"), 127 PSC_CLK(10, NULL, NULL), /* scr0; purpose and parent clk unclear */ 128 PSC_CLK(11, NULL, NULL), /* scr1; purpose and parent clk unclear */ 129 PSC_CLK(12, NULL, NULL), /* scr2; purpose and parent clk unclear */ 130 PSC_CLK(13, "pru", "pll0_sysclk2"), 131 PSC_CLK(14, "arm", "pll0_sysclk6"), 132 }; 133 134 static struct am18xx_psc_clk am18xx_psc1_clks[] = { 135 PSC_CLK(0, "edma1_cc0", "pll0_sysclk2"), 136 PSC_CLK(1, "usb2_0", "pll0_sysclk2"), 137 PSC_CLK(2, "usb1_1", "pll0_sysclk4"), 138 PSC_CLK(3, "gpio", "pll0_sysclk4"), 139 PSC_CLK(4, "hpi", "pll0_sysclk2"), 140 PSC_CLK(5, "emac", "pll0_sysclk4"), 141 PSC_CLK(6, "ddr", "pll0_sysclk2"), 142 PSC_CLK(7, "mcasp0", "async3"), 143 PSC_CLK(8, "sata", "pll0_sysclk2"), 144 PSC_CLK(9, "vpif", "pll0_sysclk2"), 145 PSC_CLK(10, "spi1", "async3"), 146 PSC_CLK(11, "i2c1", "pll0_sysclk4"), 147 PSC_CLK(12, "uart1", "async3"), 148 PSC_CLK(13, "uart2", "async3"), 149 PSC_CLK(14, "mcbsp0", "async3"), 150 PSC_CLK(15, "mcbsp1", "async3"), 151 PSC_CLK(16, "lcdc", "pll0_sysclk2"), 152 PSC_CLK(17, "ehrpwm", "async3"), 153 PSC_CLK(18, "sdmmc1", "pll0_sysclk2"), 154 PSC_CLK(19, "upp", "pll0_sysclk2"), 155 PSC_CLK(20, "ecap", "async3"), 156 PSC_CLK(21, "edma1_tc0", "pll0_sysclk2"), 157 }; 158 159 static const struct am18xx_psc_config am18xx_psc0_config = { 160 .clks = am18xx_psc0_clks, 161 .clknum = __arraycount(am18xx_psc0_clks) 162 }; 163 164 static const struct am18xx_psc_config am18xx_psc1_config = { 165 .clks = am18xx_psc1_clks, 166 .clknum = __arraycount(am18xx_psc1_clks) 167 }; 168 169 static const struct device_compatible_entry compat_data[] = { 170 { .compat = "ti,da850-psc0", .data = &am18xx_psc0_config }, 171 { .compat = "ti,da850-psc1", .data = &am18xx_psc1_config }, 172 DEVICE_COMPAT_EOL 173 }; 174 175 static const struct fdtbus_clock_controller_func am18xx_psc_clk_fdt_funcs = { 176 .decode = am18xx_psc_decode, 177 }; 178 179 static const struct clk_funcs am18xx_psc_clk_funcs = { 180 .get = am18xx_psc_clk_get, 181 .get_rate = am18xx_psc_clk_get_rate, 182 .enable = am18xx_psc_clk_enable, 183 .disable = am18xx_psc_clk_disable, 184 .get_parent = am18xx_psc_clk_get_parent 185 }; 186 187 static const struct fdtbus_powerdomain_controller_func am18xx_psc_pdom_funcs = { 188 .pdc_enable = am18xx_psc_powerdomain_enable 189 }; 190 191 static void 192 am18xx_psc_powerdomain_enable(device_t dev, const uint32_t *data, bool enable) 193 { 194 struct am18xx_psc_softc * const sc = device_private(dev); 195 uint32_t index = be32toh(data[1]); 196 197 KASSERT(index < sc->sc_clknum); 198 199 /* parts of the DTB use powerdomains as if they are clocks */ 200 struct clk *powerdomain_clk = &sc->sc_clks[index].clk_base; 201 if (enable) { 202 am18xx_psc_clk_enable(sc, powerdomain_clk); 203 } else { 204 am18xx_psc_clk_disable(sc, powerdomain_clk); 205 } 206 } 207 208 /* should be called with sc->sc_lock held */ 209 static void 210 am18xx_psc_clk_transition(struct am18xx_psc_softc *sc, 211 struct am18xx_psc_clk *clk, uint32_t state) 212 { 213 /* update clock gate state */ 214 uint32_t mdctl_reg = AM18XX_PSC_MDCTL0 + 4*clk->clk_index; 215 PSC_WRITE(sc, mdctl_reg, state); 216 PSC_WRITE(sc, AM18XX_PSC_PTCMD, AM18XX_PSC_PTCMD_GO_ALL); 217 218 /* wait for clock state transition to finish */ 219 while (PSC_READ(sc, AM18XX_PSC_PTSTAT) & AM18XX_PSC_PTSTAT_MASK) 220 continue; 221 } 222 223 static struct clk * 224 am18xx_psc_clk_get(void *priv, const char *name) 225 { 226 struct am18xx_psc_softc * const sc = priv; 227 228 for (int i = 0; i < sc->sc_clknum; i++) { 229 if (strcmp(sc->sc_clks[i].clk_base.name, name) == 0) 230 return &sc->sc_clks[i].clk_base; 231 } 232 233 return NULL; 234 } 235 236 static u_int 237 am18xx_psc_clk_get_rate(void *priv, struct clk *clkp) 238 { 239 struct am18xx_psc_clk *clk = (struct am18xx_psc_clk *)clkp; 240 241 /* The PSC is only for clock gates, rates are passed through */ 242 return clk_get_rate(clk->u.clk_parent); 243 } 244 245 static int 246 am18xx_psc_clk_enable(void *priv, struct clk *clkp) 247 { 248 struct am18xx_psc_softc * const sc = priv; 249 struct am18xx_psc_clk *clk = (struct am18xx_psc_clk *)clkp; 250 251 mutex_enter(&sc->sc_lock); 252 253 clk->clk_refcount += 1; 254 255 am18xx_psc_clk_transition(sc, clk, AM18XX_PSC_MDCTL_ENABLE); 256 257 mutex_exit(&sc->sc_lock); 258 259 return 0; 260 } 261 262 static int 263 am18xx_psc_clk_disable(void *priv, struct clk *clkp) 264 { 265 struct am18xx_psc_softc * const sc = priv; 266 struct am18xx_psc_clk *clk = (struct am18xx_psc_clk *)clkp; 267 268 mutex_enter(&sc->sc_lock); 269 270 KASSERT(clk->clk_refcount > 0); 271 clk->clk_refcount -= 1; 272 273 if (clk->clk_refcount == 0) { 274 am18xx_psc_clk_transition(sc, clk, AM18XX_PSC_MDCTL_DISABLE); 275 } 276 277 mutex_exit(&sc->sc_lock); 278 279 return 0; 280 } 281 282 static struct clk * 283 am18xx_psc_clk_get_parent(void *priv, struct clk *clkp) 284 { 285 struct am18xx_psc_clk *clk = (struct am18xx_psc_clk *)clkp; 286 287 return clk->u.clk_parent; 288 } 289 290 static struct clk * 291 am18xx_psc_decode(device_t dev, int cc_phandle, const void *data, size_t len) 292 { 293 struct am18xx_psc_softc * const sc = device_private(dev); 294 const u_int *cells = data; 295 296 if (len != 4) 297 return NULL; 298 const u_int clock_index = be32toh(cells[0]); 299 300 if (clock_index >= sc->sc_clknum) 301 return NULL; 302 303 struct am18xx_psc_clk *clk = &sc->sc_clks[clock_index]; 304 305 return &clk->clk_base; 306 } 307 308 int 309 am18xx_psc_match(device_t parent, cfdata_t cf, void *aux) 310 { 311 struct fdt_attach_args * const faa = aux; 312 313 return of_compatible_match(faa->faa_phandle, compat_data); 314 } 315 316 void 317 am18xx_psc_attach(device_t parent, device_t self, void *aux) 318 { 319 struct am18xx_psc_softc * const sc = device_private(self); 320 struct fdt_attach_args * const faa = aux; 321 const int phandle = faa->faa_phandle; 322 bus_addr_t addr; 323 bus_size_t size; 324 const struct am18xx_psc_config *config; 325 326 sc->sc_bst = faa->faa_bst; 327 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 328 329 /* map PSC control registers */ 330 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 331 aprint_error(": couldn't get registers\n"); 332 return; 333 } 334 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 335 aprint_error(": couldn't map registers\n"); 336 return; 337 } 338 339 /* initialize clock domain */ 340 sc->sc_clkdom.name = device_xname(self); 341 sc->sc_clkdom.funcs = &am18xx_psc_clk_funcs; 342 sc->sc_clkdom.priv = sc; 343 344 /* wire up different clock tables depending on if it is psc0 or psc1 */ 345 config = of_compatible_lookup(phandle, compat_data)->data; 346 sc->sc_clks = config->clks; 347 sc->sc_clknum = config->clknum; 348 349 /* get parent clock, then attach the clk gate */ 350 for (int i = 0; i < sc->sc_clknum; i++) { 351 /* skip unused clock gates */ 352 if (sc->sc_clks[i].clk_base.name == NULL) 353 continue; 354 355 struct clk *parent_clk = 356 fdtbus_clock_get(phandle, sc->sc_clks[i].u.clk_parent_name); 357 if (parent_clk == NULL) { 358 aprint_error(": couldn't get clock parent for %s\n", 359 sc->sc_clks[i].clk_base.name); 360 return; 361 } 362 sc->sc_clks[i].u.clk_parent = parent_clk; 363 sc->sc_clks[i].clk_base.domain = &sc->sc_clkdom; 364 365 clk_attach(&sc->sc_clks[i].clk_base); 366 } 367 368 /* register it in the fdt subsystem */ 369 fdtbus_register_clock_controller(self, phandle, 370 &am18xx_psc_clk_fdt_funcs); 371 fdtbus_register_powerdomain_controller(self, phandle, 372 &am18xx_psc_pdom_funcs); 373 374 aprint_normal("\n"); 375 } 376 377
Indexes created Sun Oct 25 00:26:45 UTC 2026