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    Searched defs:GATE_PARENT (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/arch/arm/amlogic/
mesongxbb_aoclkc.c 45 #define GATE_PARENT "mpeg-clk"
69 MESON_CLK_GATE(MESONGXBB_CLOCK_AO_REMOTE, "remote_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 0),
70 MESON_CLK_GATE(MESONGXBB_CLOCK_AO_I2C_MASTER, "i2c_master_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 1),
71 MESON_CLK_GATE(MESONGXBB_CLOCK_AO_I2C_SLAVE, "i2c_slave_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 2),
72 MESON_CLK_GATE(MESONGXBB_CLOCK_AO_UART1, "uart1_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 3),
73 MESON_CLK_GATE(MESONGXBB_CLOCK_AO_UART2, "uart2_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 5),
74 MESON_CLK_GATE(MESONGXBB_CLOCK_AO_IR_BLASTER, "ir_blaster_ao", GATE_PARENT, AO_RTI_GEN_CTNL_REG0, 6),
mesong12_aoclkc.c 46 #define GATE_PARENT "mpeg-clk"
71 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 0),
73 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 1),
75 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 2),
77 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 3),
79 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 4),
81 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 5),
83 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 6),
85 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 7),
87 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 8)
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