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    Searched defs:GETREG (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/arch/mips/alchemy/dev/
aurtc.c 88 #define GETREG(x) (REGVAL(x))
144 tv->tv_sec = GETREG(PC_COUNTER_READ_0);
160 while (GETREG(PC_COUNTER_CONTROL) & CC_C0S) {
180 while (GETREG(PC_COUNTER_CONTROL) & CC_C0S) {
augpio.c 72 #define GETREG(x) \
77 #define GETGPIO(x) GETREG(GPIO_BASE + (x))
79 #define GETGPIO2(x) GETREG(GPIO2_BASE + (x))
auspi.c 106 #define GETREG(sc, x) \
175 reg = GETREG(sc, AUPSC_SPICFG);
240 if (GETREG(sc, AUPSC_SPISTAT) & SPISTAT_DR) {
260 if (GETREG(sc, AUPSC_SPISTAT) & SPISTAT_TF) {
294 if ((GETREG(sc, AUPSC_SPISTAT) & SPISTAT_RE) != 0) {
299 data = GETREG(sc, AUPSC_SPITXRX);
368 if ((GETREG(sc, AUPSC_SPISTAT) & SPISTAT_DI) == 0) {
372 ev = GETREG(sc, AUPSC_SPIEVNT);
  /src/sys/arch/mips/cavium/dev/
octeon_mpi.c 80 #define GETREG(sc, x) \
230 return GETREG(sc, offset);
  /src/sys/arch/arm/at91/
at91spi.c 97 #define GETREG(sc, x) \
186 if (GETREG(sc, SPI_SR) & SPI_SR_RDRF)
187 (void)GETREG(sc, SPI_RDR);
205 csr = GETREG(sc, SPI_CSR(0)); /* read register */
252 if (GETREG(sc, AUPSC_SPISTAT) & SPISTAT_DR) {
275 if (((sr = GETREG(sc, SPI_SR)) & (SPI_SR_ENDTX | SPI_SR_ENDRX)) != (SPI_SR_ENDTX | SPI_SR_ENDRX)) {
339 GETREG(sc, SPI_MR), GETREG(sc, SPI_SR),
340 GETREG(sc, SPI_IMR), GETREG(sc, SPI_CSR(0))))
    [all...]
  /src/sys/arch/mips/atheros/dev/
argpio.c 91 #define GETREG(sc, o) bus_space_read_4(sc->sc_st, sc->sc_sh, o)
168 reg = GETREG(sc, GPIO_CR);
217 reg = GETREG(sc, GPIO_CR);
239 reg = GETREG(sc, GPIO_DO);
253 return ((GETREG(sc, GPIO_DI) & (1 << pin)) ?
268 GETREG(sc, GPIO_CR) | INTR(sc->sc_rstpin));
281 PUTREG(sc, GPIO_CR, GETREG(sc, GPIO_CR) & ~INTR(sc->sc_rstpin));
arspi.c 132 #define GETREG(sc, o) bus_space_read_4(sc->sc_st, sc->sc_sh, o)
219 while (GETREG(sc, ARSPI_REG_CTL) & ARSPI_CTL_BUSY);
301 ctl = GETREG(sc, ARSPI_REG_CTL);
354 if ((GETREG(sc, ARSPI_REG_DATA) &
375 job->job_data = GETREG(sc, ARSPI_REG_DATA);
  /src/sys/dev/marvell/
mvspi.c 78 #define GETREG(sc, x) \
126 ctl = GETREG(sc, MVSPI_INTCONF_REG);
273 ctl = GETREG(sc, MVSPI_CTRL_REG);
281 int ctl = GETREG(sc, MVSPI_CTRL_REG);
312 ctl = GETREG(sc, MVSPI_CTRL_REG);
327 if (GETREG(sc, MVSPI_CTRL_REG) &
344 GETREG(sc, MVSPI_DATAIN_REG);
  /src/sys/dev/ic/
smc90cx6.c 136 #define GETREG(off) bus_space_read_1(bst_r, regs, (off))
163 } while (!(GETREG(BAHSTAT) & BAH_POR));
261 } while (!(GETREG(BAHSTAT) & BAH_POR));
280 device_xname(sc->sc_dev), GETREG(BAHSTAT));
286 device_xname(sc->sc_dev), GETREG(BAHSTAT));
302 device_xname(sc->sc_dev), GETREG(BAHSTAT));
692 device_xname(sc->sc_dev), buffer, GETREG(BAHSTAT));
703 device_xname(sc->sc_dev), GETREG(BAHSTAT));
733 isr = GETREG(BAHSTAT);
832 GETREG(BAHSTAT))
    [all...]
  /src/sys/arch/arm/rockchip/
rk3399_pcie.c 43 #define GETREG(m, v) (__SHIFTOUT((v), (m)))

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