1 /* $NetBSD: gtreg.h,v 1.7 2021/11/10 17:19:30 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DISCOVERY_DEV_GTREG_H_ 41 #define _DISCOVERY_DEV_GTREG_H_ 42 43 #define GT__BIT(bit) (1U << (bit)) 44 #define GT__MASK(bit) (GT__BIT(bit) - 1) 45 #define GT__EXT(data, bit, len) (((data) >> (bit)) & GT__MASK(len)) 46 #define GT__CLR(data, bit, len) ((data) &= ~(GT__MASK(len) << (bit))) 47 #define GT__INS(new, bit) ((new) << (bit)) 48 49 #define GT_SIZE 0x10000 50 51 /* 52 * Table 30: CPU Address Decode Register Map 53 */ 54 #define GT_SCS0_Low_Decode 0x0008 55 #define GT_SCS0_High_Decode 0x0010 56 #define GT_SCS1_Low_Decode 0x0208 57 #define GT_SCS1_High_Decode 0x0210 58 #define GT_SCS2_Low_Decode 0x0018 59 #define GT_SCS2_High_Decode 0x0020 60 #define GT_SCS3_Low_Decode 0x0218 61 #define GT_SCS3_High_Decode 0x0220 62 #define GT_CS0_Low_Decode 0x0028 63 #define GT_CS0_High_Decode 0x0030 64 #define GT_CS1_Low_Decode 0x0228 65 #define GT_CS1_High_Decode 0x0230 66 #define GT_CS2_Low_Decode 0x0248 67 #define GT_CS2_High_Decode 0x0250 68 #define GT_CS3_Low_Decode 0x0038 69 #define GT_CS3_High_Decode 0x0040 70 #define GT_BootCS_Low_Decode 0x0238 71 #define GT_BootCS_High_Decode 0x0240 72 #define GT_PCI0_IO_Low_Decode 0x0048 73 #define GT_PCI0_IO_High_Decode 0x0050 74 #define GT_PCI0_Mem0_Low_Decode 0x0058 75 #define GT_PCI0_Mem0_High_Decode 0x0060 76 #define GT_PCI0_Mem1_Low_Decode 0x0080 77 #define GT_PCI0_Mem1_High_Decode 0x0088 78 #define GT_PCI0_Mem2_Low_Decode 0x0258 79 #define GT_PCI0_Mem2_High_Decode 0x0260 80 #define GT_PCI0_Mem3_Low_Decode 0x0280 81 #define GT_PCI0_Mem3_High_Decode 0x0288 82 #define GT_PCI1_IO_Low_Decode 0x0090 83 #define GT_PCI1_IO_High_Decode 0x0098 84 #define GT_PCI1_Mem0_Low_Decode 0x00a0 85 #define GT_PCI1_Mem0_High_Decode 0x00a8 86 #define GT_PCI1_Mem1_Low_Decode 0x00b0 87 #define GT_PCI1_Mem1_High_Decode 0x00b8 88 #define GT_PCI1_Mem2_Low_Decode 0x02a0 89 #define GT_PCI1_Mem2_High_Decode 0x02a8 90 #define GT_PCI1_Mem3_Low_Decode 0x02b0 91 #define GT_PCI1_Mem3_High_Decode 0x02b8 92 #define GT_Internal_Decode 0x0068 93 #define GT_CPU0_Low_Decode 0x0290 94 #define GT_CPU0_High_Decode 0x0298 95 #define GT_CPU1_Low_Decode 0x02c0 96 #define GT_CPU1_High_Decode 0x02c8 97 #define GT_PCI0_IO_Remap 0x00f0 98 #define GT_PCI0_Mem0_Remap_Low 0x00f8 99 #define GT_PCI0_Mem0_Remap_High 0x0320 100 #define GT_PCI0_Mem1_Remap_Low 0x0100 101 #define GT_PCI0_Mem1_Remap_High 0x0328 102 #define GT_PCI0_Mem2_Remap_Low 0x02f8 103 #define GT_PCI0_Mem2_Remap_High 0x0330 104 #define GT_PCI0_Mem3_Remap_Low 0x0300 105 #define GT_PCI0_Mem3_Remap_High 0x0338 106 #define GT_PCI1_IO_Remap 0x0108 107 #define GT_PCI1_Mem0_Remap_Low 0x0110 108 #define GT_PCI1_Mem0_Remap_High 0x0340 109 #define GT_PCI1_Mem1_Remap_Low 0x0118 110 #define GT_PCI1_Mem1_Remap_High 0x0348 111 #define GT_PCI1_Mem2_Remap_Low 0x0310 112 #define GT_PCI1_Mem2_Remap_High 0x0350 113 #define GT_PCI1_Mem3_Remap_Low 0x0318 114 #define GT_PCI1_Mem3_Remap_High 0x0358 115 116 117 /* 118 * Table 31: CPU Control Register Map 119 */ 120 #define GT_CPU_Cfg 0x0000 121 #define GT_CPU_Mode 0x0120 122 #define GT_CPU_Master_Ctl 0x0160 123 #define GT_CPU_If_Xbar_Ctl_Low 0x0150 124 #define GT_CPU_If_Xbar_Ctl_High 0x0158 125 #define GT_CPU_If_Xbar_Timeout 0x0168 126 #define GT_CPU_Rd_Rsp_Xbar_Ctl_Low 0x0170 127 #define GT_CPU_Rd_Rsp_Xbar_Ctl_High 0x0178 128 129 /* 130 * Table 32: CPU Sync Barrier Register Map 131 */ 132 #define GT_PCI_Sync_Barrier(bus) (0x00c0 | ((bus) << 3)) 133 #define GT_PCI0_Sync_Barrier 0x00c0 134 #define GT_PCI1_Sync_Barrier 0x00c8 135 136 /* 137 * Table 33: CPU Access Protection Register Map 138 */ 139 #define GT_Protect_Low_0 0x0180 140 #define GT_Protect_High_0 0x0188 141 #define GT_Protect_Low_1 0x0190 142 #define GT_Protect_High_1 0x0198 143 #define GT_Protect_Low_2 0x01a0 144 #define GT_Protect_High_2 0x01a8 145 #define GT_Protect_Low_3 0x01b0 146 #define GT_Protect_High_3 0x01b8 147 #define GT_Protect_Low_4 0x01c0 148 #define GT_Protect_High_4 0x01c8 149 #define GT_Protect_Low_5 0x01d0 150 #define GT_Protect_High_5 0x01d8 151 #define GT_Protect_Low_6 0x01e0 152 #define GT_Protect_High_6 0x01e8 153 #define GT_Protect_Low_7 0x01f0 154 #define GT_Protect_High_7 0x01f8 155 156 /* 157 * Table 34: Snoop Control Register Map 158 */ 159 #define GT_Snoop_Base_0 0x0380 160 #define GT_Snoop_Top_0 0x0388 161 #define GT_Snoop_Base_1 0x0390 162 #define GT_Snoop_Top_1 0x0398 163 #define GT_Snoop_Base_2 0x03a0 164 #define GT_Snoop_Top_2 0x03a8 165 #define GT_Snoop_Base_3 0x03b0 166 #define GT_Snoop_Top_3 0x03b8 167 168 /* 169 * Table 35: CPU Error Report Register Map 170 */ 171 #define GT_CPU_Error_Address_Low 0x0070 172 #define GT_CPU_Error_Address_High 0x0078 173 #define GT_CPU_Error_Data_Low 0x0128 174 #define GT_CPU_Error_Data_High 0x0130 175 #define GT_CPU_Error_Parity 0x0138 176 #define GT_CPU_Error_Cause 0x0140 177 #define GT_CPU_Error_Mask 0x0148 178 179 #define GT_LowAddr_GET(v) (GT__EXT((v), 0, 12) << 20) 180 #define GT_HighAddr_GET(v) \ 181 ((v) != 0 ? ((GT__EXT((v), 0, 12) << 20) | 0xfffff) : 0) 182 #define GT_LowAddr2_GET(v) (GT__EXT((v), 0, 16) << 16) 183 #define GT_HighAddr2_GET(v) \ 184 ((v) != 0 ? ((GT__EXT((v), 0, 16) << 16) | 0xffff) : 0) 185 #define GT_LADDR_GET(v, mdl) \ 186 (((mdl) == MARVELL_DISCOVERY) ? GT_LowAddr_GET(v) : GT_LowAddr2_GET(v)) 187 #define GT_HADDR_GET(v, mdl) \ 188 (((mdl) == MARVELL_DISCOVERY) ? GT_HighAddr_GET(v) : GT_HighAddr2_GET(v)) 189 190 #define GT_MPP_Control0 0xf000 191 #define GT_MPP_Control1 0xf004 192 #define GT_MPP_Control2 0xf008 193 #define GT_MPP_Control3 0xf00c 194 195 #define GT_GPP_IO_Control 0xf100 196 #define GT_GPP_Value 0xf104 197 #define GT_GPP_Interrupt_Cause 0xf108 198 #define GT_GPP_Interrupt_Mask 0xf10c 199 #define GT_GPP_Level_Control 0xf110 200 #define GT_GPP_Interrupt_Mask1 0xf114 201 #define GT_GPP_Value_Set 0xf118 202 #define GT_GPP_Value_Clear 0xf11c 203 /* 204 * Table 36: SCS[0]* Low Decode Address, Offset: 0x008 205 * Table 38: SCS[1]* Low Decode Address, Offset: 0x208 206 * Table 40: SCS[2]* Low Decode Address, Offset: 0x018 207 * Table 42: SCS[3]* Low Decode Address, Offset: 0x218 208 * Table 44: CS[0]* Low Decode Address, Offset: 0x028 209 * Table 46: CS[1]* Low Decode Address, Offset: 0x228 210 * Table 48: CS[2]* Low Decode Address, Offset: 0x248 211 * Table 50: CS[3]* Low Decode Address, Offset: 0x038 212 * Table 52: BootCS* Low Decode Address, Offset: 0x238 213 * Table 75: CPU 0 Low Decode Address, Offset: 0x290 214 * Table 77: CPU 1 Low Decode Address, Offset: 0x2c0 215 * 216 * 11:00 LowAddr SCS[0] Base Address 217 * 31:12 Reserved Must be 0. 218 */ 219 220 /* 221 * Table 37: SCS[0]* High Decode Address, Offset: 0x010 222 * Table 39: SCS[1]* High Decode Address, Offset: 0x210 223 * Table 41: SCS[2]* High Decode Address, Offset: 0x020 224 * Table 43: SCS[3]* High Decode Address, Offset: 0x220 225 * Table 45: CS[0]* High Decode Address, Offset: 0x030 226 * Table 47: CS[1]* High Decode Address, Offset: 0x230 227 * Table 49: CS[2]* High Decode Address, Offset: 0x250 228 * Table 51: CS[3]* High Decode Address, Offset: 0x040 229 * Table 53: BootCS* High Decode Address, Offset: 0x240 230 * Table 76: CPU 0 High Decode Address, Offset: 0x298 231 * Table 78: CPU 1 High Decode Address, Offset: 0x2c8 232 * 233 * 11:00 HighAddr SCS[0] Top Address 234 * 31:12 Reserved 235 */ 236 237 /* 238 * Table 54: PCI_0 I/O Low Decode Address, Offset: 0x048 239 * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058 240 * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080 241 * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258 242 * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280 243 * Table 64: PCI_1 I/O Low Decode Address, Offset: 0x090 244 * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0 245 * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0 246 * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0 247 * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0 248 * 249 * 11:00 LowAddr PCI IO/Memory Space Base Address 250 * 23:12 Reserved 251 * 26:24 PCISwap PCI Master Data Swap Control (0: Byte Swap; 252 * 1: No swapping; 2: Both byte and word swap; 253 * 3: Word swap; 4..7: Reserved) 254 * 27:27 PCIReq64 PCI master REQ64* policy (Relevant only when 255 * configured to 64-bit PCI bus and not I/O) 256 * 0: Assert s REQ64* only when transaction 257 * is longer than 64-bits. 258 * 1: Always assert REQ64*. 259 * 31:28 Reserved 260 */ 261 #define GT_PCISwap_GET(v) GT__EXT((v), 24, 3) 262 #define GT_PCISwap_ByteSwap 0 263 #define GT_PCISwap_NoSwap 1 264 #define GT_PCISwap_ByteWordSwap 2 265 #define GT_PCISwap_WordSwap 3 266 #define GT_PCI_LowDecode_PCIReq64 GT__BIT(27) 267 268 /* 269 * Table 55: PCI_0 I/O High Decode Address, Offset: 0x050 270 * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060 271 * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088 272 * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260 273 * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288 274 * Table 65: PCI_1 I/O High Decode Address, Offset: 0x098 275 * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8 276 * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8 277 * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8 278 * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8 279 * 280 * 11:00 HighAddr PCI_0 I/O Space Top Address 281 * 31:12 Reserved 282 */ 283 284 /* 285 * Table 74: Internal Space Decode, Offset: 0x068 286 * 15:00 IntDecode GT64260 Internal Space Base Address 287 * 23:16 Reserved 288 * 26:24 PCISwap Same as PCI_0 Memory 0 Low Decode Address. 289 * NOTE: Reserved for Galileo Technology usage. 290 * Relevant only for PCI master configuration 291 * transactions on the PCI bus. 292 * 31:27 Reserved 293 */ 294 295 /* 296 * Table 79: PCI_0 I/O Address Remap, Offset: 0x0f0 297 * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8 298 * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100 299 * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8 300 * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300 301 * Table 88: PCI_1 I/O Address Remap, Offset: 0x108 302 * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110 303 * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118 304 * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310 305 * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318 306 * 307 * 11:00 Remap PCI IO/Memory Space Address Remap (31:20) 308 * 31:12 Reserved 309 */ 310 311 /* 312 * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320 313 * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328 314 * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330 315 * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338 316 * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340 317 * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348 318 * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350 319 * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358 320 * 321 * 31:00 Remap PCI Memory Address Remap (high 32 bits) 322 */ 323 324 /* 325 * Table 97: CPU Configuration, Offset: 0x000 326 * 07:00 NoMatchCnt CPU Address Miss Counter 327 * 08:08 NoMatchCntEn CPU Address Miss Counter Enable 328 * NOTE: Relevant only if multi-GT is enabled. 329 * (0: Disabled; 1: Enabled) 330 * 09:09 NoMatchCntExt CPU address miss counter MSB 331 * 10:10 Reserved 332 * 11:11 AACKDelay Address Acknowledge Delay 333 * 0: AACK* is asserted one cycle after TS*. 334 * 1: AACK* is asserted two cycles after TS*. 335 * 12:12 Endianness Must be 0 336 * NOTE: The GT64260 does not support the PowerPC 337 * Little Endian convention 338 * 13:13 Pipeline Pipeline Enable 339 * 0: Disabled. The GT64260 will not respond with 340 * AACK* to a new CPU transaction, before the 341 * previous transaction data phase completes. 342 * 1: Enabled. 343 * 14:14 Reserved 344 * 15:15 TADelay Transfer Acknowledge Delay 345 * 0: TA* is asserted one cycle after AACK* 346 * 1: TA* is asserted two cycles after AACK* 347 * 16:16 RdOOO Read Out of Order Completion 348 * 0: Not Supported, Data is always returned in 349 * order (DTI[0-2] is always driven 350 * 1: Supported 351 * 17:17 StopRetry Relevant only if PCI Retry is enabled 352 * 0: Keep Retry all PCI transactions targeted 353 * to the GT64260. 354 * 1: Stop Retry of PCI transactions. 355 * 18:18 MultiGTDec Multi-GT Address Decode 356 * 0: Normal address decoding 357 * 1: Multi-GT address decoding 358 * 19:19 DPValid CPU DP[0-7] Connection. CPU write parity ... 359 * 0: is not checked. (Not connected) 360 * 1: is checked (Connected) 361 * 21:20 Reserved 362 * 22:22 PErrProp Parity Error Propagation 363 * 0: GT64260 always drives good parity on 364 * DP[0-7] during CPU reads. 365 * 1: GT64260 drives bad parity on DP[0-7] in case 366 * the read response from the target interface 367 * comes with erroneous data indication 368 * (e.g. ECC error from SDRAM interface). 369 * 25:23 Reserved 370 * 26:26 APValid CPU AP[0-3] Connection. CPU address parity ... 371 * 0: is not checked. (Not connected) 372 * 1: is checked (Connected) 373 * 27:27 RemapWrDis Address Remap Registers Write Control 374 * 0: Write to Low Address decode register. 375 * Results in writing of the corresponding 376 * Remap register. 377 * 1: Write to Low Address decode register. No 378 * effect on the corresponding Remap register. 379 * 28:28 ConfSBDis Configuration Read Sync Barrier Disable 380 * 0: enabled; 1: disabled 381 * 29:29 IOSBDis I/O Read Sync Barrier Disable 382 * 0: enabled; 1: disabled 383 * 30:30 ClkSync Clocks Synchronization 384 * 0: The CPU interface is running with SysClk, 385 * which is asynchronous to TClk. 386 * 1: The CPU interface is running with TClk. 387 * 31:31 Reserved 388 */ 389 #define GT_CPUCfg_NoMatchCnt_GET(v) GT__EXT((v), 0, 8) 390 #define GT_CPUCfg_NoMatchCntEn GT__BIT( 9) 391 #define GT_CPUCfg_NoMatchCntExt GT__BIT(10) 392 #define GT_CPUCfg_AACKDelay GT__BIT(11) 393 #define GT_CPUCfg_Endianness GT__BIT(12) 394 #define GT_CPUCfg_Pipeline GT__BIT(13) 395 #define GT_CPUCfg_TADelay GT__BIT(15) 396 #define GT_CPUCfg_RdOOO GT__BIT(16) 397 #define GT_CPUCfg_StopRetry GT__BIT(17) 398 #define GT_CPUCfg_MultiGTDec GT__BIT(18) 399 #define GT_CPUCfg_DPValid GT__BIT(19) 400 #define GT_CPUCfg_PErrProp GT__BIT(22) 401 #define GT_CPUCfg_APValid GT__BIT(26) 402 #define GT_CPUCfg_RemapWrDis GT__BIT(27) 403 #define GT_CPUCfg_ConfSBDis GT__BIT(28) 404 #define GT_CPUCfg_IOSBDis GT__BIT(29) 405 #define GT_CPUCfg_ClkSync GT__BIT(30) 406 407 /* 408 * Table 98: CPU Mode, Offset: 0x120, Read only 409 * 01:00 MultiGTID Multi-GT ID 410 * Represents the ID to which the GT64260 responds 411 * to during a multi-GT address decoding period. 412 * 02:02 MultiGT (0: Single; 1: Multiple) GT configuration 413 * 03:03 RetryEn (0: Don't; 1: Do) Retry PCI transactions 414 * 07:04 CPUType 415 * 0x0-0x3: Reserved 416 * 0x4: 64-bit PowerPC CPU, 60x bus 417 * 0x5: 64-bit PowerPC CPU, MPX bus 418 * 0x6-0xf: Reserved 419 * 31:08 Reserved 420 */ 421 #define GT_CPUMode_MultiGTID_GET(v) GT__EXT(v, 0, 2) 422 #define GT_CPUMode_MultiGT GT__BIT(2) 423 #define GT_CPUMode_RetryEn GT__BIT(3) 424 #define GT_CPUMode_CPUType_GET(v) GT__EXT(v, 4, 4) 425 426 /* 427 * Table 99: CPU Master Control, Offset: 0x160 428 * 07:00 Reserved 429 * 08:08 IntArb CPU Bus Internal Arbiter Enable 430 * NOTE: Only relevant to 60x bus mode. When 431 * running MPX bus, the GT64260 internal 432 * arbiter must be used. 433 * 0: Disabled. External arbiter is required. 434 * 1: Enabled. Use the GT64260 CPU bus arbiter. 435 * 09:09 IntBusCtl CPU Interface Unit Internal Bus Control 436 * NOTE: This bit must be set to 1. It is reserved 437 * for Galileo Technology usage. 438 * 0: Enable internal bus sharing between master 439 * and slave interfaces. 440 * 1: Disable internal bus sharing between master 441 * and slave interfaces. 442 * 10:10 MWrTrig Master Write Transaction Trigger 443 * 0: With first valid write data 444 * 1: With last valid write data 445 * 11:11 MRdTrig Master Read Response Trigger 446 * 0: With first valid read data 447 * 1: With last valid read data 448 * 12:12 CleanBlock Clean Block Snoop Transaction Support 449 * 0: CPU does not support clean block (603e,750) 450 * 1: CPU supports clean block (604e,G4) 451 * 13:13 FlushBlock Flush Block Snoop Transaction Support 452 * 0: CPU does not support flush block (603e,750) 453 * 1: CPU supports flush block (604e,G4) 454 * 31:14 Reserved 455 */ 456 #define GT_CPUMstrCtl_IntArb GT__BIT(8) 457 #define GT_CPUMstrCtl_IntBusCtl GT__BIT(9) 458 #define GT_CPUMstrCtl_MWrTrig GT__BIT(10) 459 #define GT_CPUMstrCtl_MRdTrig GT__BIT(11) 460 #define GT_CPUMstrCtl_CleanBlock GT__BIT(12) 461 #define GT_CPUMstrCtl_FlushBlock GT__BIT(13) 462 463 #define GT_ArbSlice_SDRAM 0x0 /* SDRAM interface snoop request */ 464 #define GT_ArbSlice_DEVICE 0x1 /* Device request */ 465 #define GT_ArbSlice_NULL 0x2 /* NULL request */ 466 #define GT_ArbSlice_PCI0 0x3 /* PCI_0 access */ 467 #define GT_ArbSlice_PCI1 0x4 /* PCI_1 access */ 468 #define GT_ArbSlice_COMM 0x5 /* Comm unit access */ 469 #define GT_ArbSlice_IDMA0123 0x6 /* IDMA channels 0/1/2/3 access */ 470 #define GT_ArbSlice_IDMA4567 0x7 /* IDMA channels 4/5/6/7 access */ 471 /* 0x8-0xf: Reserved */ 472 473 /* Pass in the slice number (from 0..16) as 'n' 474 */ 475 #define GT_XbarCtl_GET_ArbSlice(v, n) GT__EXT((v), (((n) & 7)*4, 4) 476 477 /* 478 * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150 479 * 03:00 Arb0 Slice 0 of CPU Master pizza Arbiter 480 * 07:04 Arb1 Slice 1 of CPU Master pizza Arbiter 481 * 11:08 Arb2 Slice 2 of CPU Master pizza Arbiter 482 * 15:12 Arb3 Slice 3 of CPU Master pizza Arbiter 483 * 19:16 Arb4 Slice 4 of CPU Master pizza Arbiter 484 * 23:20 Arb5 Slice 5 of CPU Master pizza Arbiter 485 * 27:24 Arb6 Slice 6 of CPU Master pizza Arbiter 486 * 31:28 Arb7 Slice 7 of CPU Master pizza Arbiter 487 */ 488 489 /* 490 * Table 101: CPU Interface Crossbar Control High, Offset: 0x158 491 * 03:00 Arb8 Slice 8 of CPU Master pizza Arbiter 492 * 07:04 Arb9 Slice 9 of CPU Master pizza Arbiter 493 * 11:08 Arb10 Slice 10 of CPU Master pizza Arbiter 494 * 15:12 Arb11 Slice 11 of CPU Master pizza Arbiter 495 * 19:16 Arb12 Slice 12 of CPU Master pizza Arbiter 496 * 23:20 Arb13 Slice 13 of CPU Master pizza Arbiter 497 * 27:24 Arb14 Slice 14 of CPU Master pizza Arbiter 498 * 31:28 Arb15 Slice 15 of CPU Master pizza Arbiter 499 */ 500 501 /* 502 * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168 503 * NOTE: Reserved for Galileo Technology usage. 504 * 07:00 Timeout Crossbar Arbiter Timeout Preset Value 505 * 15:08 Reserved 506 * 16:16 TimeoutEn Crossbar Arbiter Timer Enable 507 * (0: Enable; 1: Disable) 508 * 31:17 Reserved 509 */ 510 511 /* 512 * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170 513 * 03:00 Arb0 Slice 0 of CPU Slave pizza Arbiter 514 * 07:04 Arb1 Slice 1 of CPU Slave pizza Arbiter 515 * 11:08 Arb2 Slice 2 of CPU Slave pizza Arbiter 516 * 15:12 Arb3 Slice 3 of CPU Slave pizza Arbiter 517 * 19:16 Arb4 Slice 4 of CPU Slave pizza Arbiter 518 * 23:20 Arb5 Slice 5 of CPU Slave pizza Arbiter 519 * 27:24 Arb6 Slice 6 of CPU Slave pizza Arbiter 520 * 31:28 Arb7 Slice 7 of CPU Slave pizza Arbiter 521 */ 522 /* 523 * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178 524 * 03:00 Arb8 Slice 8 of CPU Slave pizza Arbiter 525 * 07:04 Arb9 Slice 9 of CPU Slave pizza Arbiter 526 * 11:08 Arb10 Slice 10 of CPU Slave pizza Arbiter 527 * 15:12 Arb11 Slice 11 of CPU Slave pizza Arbiter 528 * 19:16 Arb12 Slice 12 of CPU Slave pizza Arbiter 529 * 23:20 Arb13 Slice 13 of CPU Slave pizza Arbiter 530 * 27:24 Arb14 Slice 14 of CPU Slave pizza Arbiter 531 * 31:28 Arb15 Slice 15 of CPU Slave pizza Arbiter 532 */ 533 534 /* 535 * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0 536 * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8 537 * NOTE: The read data is random and should be ignored. 538 * 31:00 SyncBarrier A CPU read from this register creates a 539 * synchronization barrier cycle. 540 */ 541 542 /* 543 * Table 107: CPU Protect Address 0 Low, Offset: 0x180 544 * Table 109: CPU Protect Address 1 Low, Offset: 0x190 545 * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0 546 * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0 547 * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0 548 * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0 549 * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0 550 * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0 551 * 552 * 11:00 LowAddr CPU Protect Region Base Address 553 * Corresponds to address bits[31:20]. 554 * 15:12 Reserved. Must be 0 555 * 16:16 AccProtect CPU Access Protect 556 * Access is (0: allowed; 1: forbidden) 557 * 17:17 WrProtect CPU Write Protect 558 * Writes are (0: allowed; 1: forbidden) 559 * 18:18 CacheProtect CPU caching protect. Caching (block read) 560 * is (0: allowed; 1: forbidden) 561 * 31:19 Reserved 562 */ 563 #define GT_CPU_AccProtect GT__BIT(16) 564 #define GT_CPU_WrProtect GT__BIT(17) 565 #define GT_CPU_CacheProtect GT__BIT(18) 566 567 /* 568 * Table 108: CPU Protect Address 0 High, Offset: 0x188 569 * Table 110: CPU Protect Address 1 High, Offset: 0x198 570 * Table 112: CPU Protect Address 2 High, Offset: 0x1a8 571 * Table 114: CPU Protect Address 3 High, Offset: 0x1b8 572 * Table 116: CPU Protect Address 4 High, Offset: 0x1c8 573 * Table 118: CPU Protect Address 5 High, Offset: 0x1d8 574 * Table 120: CPU Protect Address 6 High, Offset: 0x1e8 575 * Table 122: CPU Protect Address 7 High, Offset: 0x1f8 576 * 577 * 11:00 HighAddr CPU Protect Region Top Address 578 * Corresponds to address bits[31:20] 579 * 31:12 Reserved 580 */ 581 582 /* 583 * Table 123: Snoop Base Address 0, Offset: 0x380 584 * Table 125: Snoop Base Address 1, Offset: 0x390 585 * Table 127: Snoop Base Address 2, Offset: 0x3a0 586 * Table 129: Snoop Base Address 3, Offset: 0x3b0 587 * 588 * 11:00 LowAddr Snoop Region Base Address [31:20] 589 * 15:12 Reserved Must be 0. 590 * 17:16 Snoop Snoop Type 591 * 0x0: No Snoop 592 * 0x1: Snoop to WT region 593 * 0x2: Snoop to WB region 594 * 0x3: Reserved 595 * 31:18 Reserved 596 */ 597 #define GT_Snoop_GET(v) GT__EXT((v), 16, 2) 598 #define GT_Snoop_INS(v) GT__INS((v), 16) 599 #define GT_Snoop_None 0 600 #define GT_Snoop_WT 1 601 #define GT_Snoop_WB 2 602 603 604 /* 605 * Table 124: Snoop Top Address 0, Offset: 0x388 606 * Table 126: Snoop Top Address 1, Offset: 0x398 607 * Table 128: Snoop Top Address 2, Offset: 0x3a8 608 * Table 130: Snoop Top Address 3, Offset: 0x3b8 609 * 11:00 HighAddr Snoop Region Top Address [31:20] 610 * 31:12 Reserved 611 */ 612 613 614 /* 615 * Table 131: CPU Error Address Low, Offset: 0x070, Read Only. 616 * In case of multiple errors, only the first one is latched. New error 617 * report latching is enabled only after the CPU Error Address Low register 618 * is being read. 619 * 31:00 ErrAddr Latched address bits [31:0] of a CPU 620 * transaction in case of: 621 * o illegal address (failed address decoding) 622 * o access protection violation 623 * o bad data parity 624 * o bad address parity 625 * Upon address latch, no new address are 626 * registered (due to additional error condition), 627 * until the register is being read. 628 */ 629 630 /* 631 * Table 132: CPU Error Address High, Offset: 0x078, Read Only. 632 * Once data is latched, no new data can be registered (due to additional 633 * error condition), until CPU Error Low Address is being read (which 634 * implies, it should be the last being read by the interrupt handler). 635 * 03:00 Reserved 636 * 07:04 ErrPar Latched address parity bits in case 637 * of bad CPU address parity detection. 638 * 31:08 Reserved 639 */ 640 #define GT_CPUErrorAddrHigh_ErrPar_GET(v) GT__EXT((v), 4, 4) 641 642 /* 643 * Table 133: CPU Error Data Low, Offset: 0x128, Read only. 644 * 31:00 PErrData Latched data bits [31:0] in case of bad data 645 * parity sampled on write transactions or on 646 * master read transactions. 647 */ 648 649 /* 650 * Table 134: CPU Error Data High, Offset: 0x130, Read only. 651 * 31:00 PErrData Latched data bits [63:32] in case of bad data 652 * parity sampled on write transactions or on 653 * master read transactions. 654 */ 655 656 /* 657 * Table 135: CPU Error Parity, Offset: 0x138, Read only. 658 * 07:00 PErrPar Latched data parity bus in case of bad data 659 * parity sampled on write transactions or on 660 * master read transactions. 661 * 31:10 Reserved 662 */ 663 #define GT_CPUErrorParity_PErrPar_GET(v) GT__EXT((v), 0, 8) 664 665 /* 666 * Table 136: CPU Error Cause, Offset: 0x140 667 * Bits[7:0] are clear only. A cause bit is set upon an error condition 668 * occurrence. Write a 0 value to clear the bit. Writing a 1 value has 669 * no effect. 670 * 00:00 AddrOut CPU Address Out of Range 671 * 01:01 AddrPErr Bad Address Parity Detected 672 * 02:02 TTErr Transfer Type Violation. 673 * The CPU attempts to burst (read or write) to an 674 * internal register. 675 * 03:03 AccErr Access to a Protected Region 676 * 04:04 WrErr Write to a Write Protected Region 677 * 05:05 CacheErr Read from a Caching protected region 678 * 06:06 WrDataPErr Bad Write Data Parity Detected 679 * 07:07 RdDataPErr Bad Read Data Parity Detected 680 * 26:08 Reserved 681 * 31:27 Sel Specifies the error event currently being 682 * reported in Error Address, Error Data, and 683 * Error Parity registers. 684 * 0x0: AddrOut 685 * 0x1: AddrPErr 686 * 0x2: TTErr 687 * 0x3: AccErr 688 * 0x4: WrErr 689 * 0x5: CacheErr 690 * 0x6: WrDataPErr 691 * 0x7: RdDataPErr 692 * 0x8-0x1f: Reserved 693 */ 694 #define GT_CPUError_AddrOut GT__BIT(GT_CPUError_Sel_AddrOut) 695 #define GT_CPUError_AddrPErr GT__BIT(GT_CPUError_Sel_AddrPErr) 696 #define GT_CPUError_TTErr GT__BIT(GT_CPUError_Sel_TTErr) 697 #define GT_CPUError_AccErr GT__BIT(GT_CPUError_Sel_AccErr) 698 #define GT_CPUError_WrErr GT__BIT(GT_CPUError_Sel_WrPErr) 699 #define GT_CPUError_CacheErr GT__BIT(GT_CPUError_Sel_CachePErr) 700 #define GT_CPUError_WrDataPErr GT__BIT(GT_CPUError_Sel_WrDataPErr) 701 #define GT_CPUError_RdDataPErr GT__BIT(GT_CPUError_Sel_RdDataPErr) 702 703 #define GT_CPUError_Sel_AddrOut 0 704 #define GT_CPUError_Sel_AddrPErr 1 705 #define GT_CPUError_Sel_TTErr 2 706 #define GT_CPUError_Sel_AccErr 3 707 #define GT_CPUError_Sel_WrErr 4 708 #define GT_CPUError_Sel_CacheErr 5 709 #define GT_CPUError_Sel_WrDataPErr 6 710 #define GT_CPUError_Sel_RdDataPErr 7 711 712 #define GT_CPUError_Sel_GET(v) GT__EXT((v), 27, 5) 713 714 /* 715 * Table 137: CPU Error Mask, Offset: 0x148 716 * 00:00 AddrOut If set to 1, enables AddrOut interrupt. 717 * 01:01 AddrPErr If set to 1, enables AddrPErr interrupt. 718 * 02:02 TTErr If set to 1, enables TTErr interrupt. 719 * 03:03 AccErr If set to 1, enables AccErr interrupt. 720 * 04:04 WrErr If set to 1, enables WrErr interrupt. 721 * 05:05 CacheErr If set to 1, enables CacheErr interrupt. 722 * 06:06 WrDataPErr If set to 1, enables WrDataPErr interrupt. 723 * 07:07 RdDataPErr If set to 1, enables RdDataPErr interrupt. 724 * 31:08 Reserved 725 */ 726 727 /* 728 * Comm Unit Interrupt registers 729 */ 730 #define GT_CommUnitIntr_Cause 0xf310 731 #define GT_CommUnitIntr_Mask 0xf314 732 #define GT_CommUnitIntr_ErrAddr 0xf318 733 734 #define GT_CommUnitIntr_E0 0x00000007 735 #define GT_CommUnitIntr_E1 0x00000070 736 #define GT_CommUnitIntr_E2 0x00000700 737 #define GT_CommUnitIntr_S0 0x00070000 738 #define GT_CommUnitIntr_S1 0x00700000 739 #define GT_CommUnitIntr_Sel 0x70000000 740 741 /* 742 * SDRAM Error Report (ECC) Registers 743 */ 744 #define GT_ECC_Data_Lo 0x484 /* latched Error Data (low) */ 745 #define GT_ECC_Data_Hi 0x480 /* latched Error Data (high) */ 746 #define GT_ECC_Addr 0x490 /* latched Error Address */ 747 #define GT_ECC_Rec 0x488 /* latched ECC code from SDRAM */ 748 #define GT_ECC_Calc 0x48c /* latched ECC code from SDRAM */ 749 #define GT_ECC_Ctl 0x494 /* ECC Control */ 750 #define GT_ECC_Count 0x498 /* ECC 1-bit error count */ 751 752 /* 753 * Watchdog Registers 754 */ 755 #define GT_WDOG_Config 0xb410 756 #define GT_WDOG_Value 0xb414 757 #define GT_WDOG_Value_NMI GT__MASK(24) 758 #define GT_WDOG_Config_Preset GT__MASK(24) 759 #define GT_WDOG_Config_Ctl1a GT__BIT(24) 760 #define GT_WDOG_Config_Ctl1b GT__BIT(25) 761 #define GT_WDOG_Config_Ctl2a GT__BIT(26) 762 #define GT_WDOG_Config_Ctl2b GT__BIT(27) 763 #define GT_WDOG_Config_Enb GT__BIT(31) 764 765 #define GT_WDOG_NMI_DFLT (GT__MASK(24) & GT_WDOG_Value_NMI) 766 #define GT_WDOG_Preset_DFLT (GT__MASK(22) & GT_WDOG_Config_Preset) 767 768 /* 769 * Device Bus Interrupts 770 */ 771 #define GT_DEVBUS_ICAUSE 0x4d0 /* Device Interrupt Cause */ 772 #define GT_DEVBUS_IMASK 0x4d4 /* Device Interrupt Mask */ 773 #define GT_DEVBUS_ERR_ADDR 0x4d8 /* Device Error Address */ 774 775 /* 776 * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK 777 */ 778 #define GT_DEVBUS_DBurstErr GT__BIT(0) 779 #define GT_DEVBUS_DRdyErr GT__BIT(1) 780 #define GT_DEVBUS_Sel GT__BIT(27) 781 #define GT_DEVBUS_RES ~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel) 782 783 784 #define ETH0_BASE 0x2400 785 #define ETH1_BASE 0x2800 786 #define ETH2_BASE 0x2c00 787 #define MPSC0_BASE 0x8000 788 #define MPSC1_BASE 0x9000 789 790 #endif /* !_DISCOVERY_DEV_GTREG_H */ 791
Indexes created Sun Sep 21 14:09:52 GMT 2025