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      1 /* $NetBSD: sun50i_h6_ccu.h,v 1.1 2018/05/01 19:53:14 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _SUN50I_H6_CCU_H
     30 #define _SUN50I_H6_CCU_H
     31 
     32 #define	H6_RST_MBUS		0
     33 #define	H6_RST_BUS_DE		1
     34 #define	H6_RST_BUS_DEINTERLACE	2
     35 #define	H6_RST_BUS_GPU		3
     36 #define	H6_RST_BUS_CE		4
     37 #define	H6_RST_BUS_VE		5
     38 #define	H6_RST_BUS_EMCE		6
     39 #define	H6_RST_BUS_VP9		7
     40 #define	H6_RST_BUS_DMA		8
     41 #define	H6_RST_BUS_MSGBOX	9
     42 #define	H6_RST_BUS_SPINLOCK	10
     43 #define	H6_RST_BUS_HSTIMER	11
     44 #define	H6_RST_BUS_DBG		12
     45 #define	H6_RST_BUS_PSI		13
     46 #define	H6_RST_BUS_PWM		14
     47 #define	H6_RST_BUS_IOMMU	15
     48 #define	H6_RST_BUS_DRAM		16
     49 #define	H6_RST_BUS_NAND		17
     50 #define	H6_RST_BUS_MMC0		18
     51 #define	H6_RST_BUS_MMC1		19
     52 #define	H6_RST_BUS_MMC2		20
     53 #define	H6_RST_BUS_UART0	21
     54 #define	H6_RST_BUS_UART1	22
     55 #define	H6_RST_BUS_UART2	23
     56 #define	H6_RST_BUS_UART3	24
     57 #define	H6_RST_BUS_I2C0		25
     58 #define	H6_RST_BUS_I2C1		26
     59 #define	H6_RST_BUS_I2C2		27
     60 #define	H6_RST_BUS_I2C3		28
     61 #define	H6_RST_BUS_SCR0		29
     62 #define	H6_RST_BUS_SCR1		30
     63 #define	H6_RST_BUS_SPI0		31
     64 #define	H6_RST_BUS_SPI1		32
     65 #define	H6_RST_BUS_EMAC		33
     66 #define	H6_RST_BUS_TS		34
     67 #define	H6_RST_BUS_IR_TX	35
     68 #define	H6_RST_BUS_THS		36
     69 #define	H6_RST_BUS_I2S0		37
     70 #define	H6_RST_BUS_I2S1		38
     71 #define	H6_RST_BUS_I2S2		39
     72 #define	H6_RST_BUS_I2S3		40
     73 #define	H6_RST_BUS_SPDIF	41
     74 #define	H6_RST_BUS_DMIC		42
     75 #define	H6_RST_BUS_AUDIO_HUB	43
     76 #define	H6_RST_USB_PHY0		44
     77 #define	H6_RST_USB_PHY1		45
     78 #define	H6_RST_USB_PHY3		46
     79 #define	H6_RST_USB_HSIC		47
     80 #define	H6_RST_BUS_OHCI0	48
     81 #define	H6_RST_BUS_OHCI3	49
     82 #define	H6_RST_BUS_EHCI0	50
     83 #define	H6_RST_BUS_XHCI		51
     84 #define	H6_RST_BUS_EHCI3	52
     85 #define	H6_RST_BUS_OTG		53
     86 #define	H6_RST_BUS_PCIE		54
     87 #define	H6_RST_PCIE_POWERUP	55
     88 #define	H6_RST_BUS_HDMI		56
     89 #define	H6_RST_BUS_HDMI_SUB	57
     90 #define	H6_RST_BUS_TCON_TOP	58
     91 #define	H6_RST_BUS_TCON_LCD0	59
     92 #define	H6_RST_BUS_TCON_TV0	60
     93 #define	H6_RST_BUS_CSI		61
     94 #define	H6_RST_BUS_HDCP		62
     95 
     96 #define	H6_CLK_OSC12M		0
     97 #define	H6_CLK_PLL_CPUX		1
     98 #define	H6_CLK_PLL_DDR0		2
     99 #define	H6_CLK_PLL_PERIPH0	3
    100 #define	H6_CLK_PLL_PERIPH0_2X	4
    101 #define	H6_CLK_PLL_PERIPH0_4X	5
    102 #define	H6_CLK_PLL_PERIPH1	6
    103 #define	H6_CLK_PLL_PERIPH1_2X	7
    104 #define	H6_CLK_PLL_PERIPH1_4X	8
    105 #define	H6_CLK_PLL_GPU		9
    106 #define	H6_CLK_PLL_VIDEO0	10
    107 #define	H6_CLK_PLL_VIDEO0_4X	11
    108 #define	H6_CLK_PLL_VIDEO1	12
    109 #define	H6_CLK_PLL_VIDEO1_4X	13
    110 #define	H6_CLK_PLL_VE		14
    111 #define	H6_CLK_PLL_DE		15
    112 #define	H6_CLK_PLL_HSIC		16
    113 #define	H6_CLK_PLL_AUDIO_BASE	17
    114 #define	H6_CLK_PLL_AUDIO	18
    115 #define	H6_CLK_PLL_AUDIO_2X	19
    116 #define	H6_CLK_PLL_AUDIO_4X	20
    117 #define	H6_CLK_CPUX		21
    118 #define	H6_CLK_AXI		22
    119 #define	H6_CLK_CPUX_APB		23
    120 #define	H6_CLK_PSI_AHB1_AHB2	24
    121 #define	H6_CLK_AHB3		25
    122 #define	H6_CLK_APB1		26
    123 #define	H6_CLK_APB2		27
    124 #define	H6_CLK_MBUS		28
    125 #define	H6_CLK_DE		29
    126 #define	H6_CLK_BUS_DE		30
    127 #define	H6_CLK_DEINTERLACE	31
    128 #define	H6_CLK_BUS_DEINTERLACE	32
    129 #define	H6_CLK_GPU		33
    130 #define	H6_CLK_BUS_GPU		34
    131 #define	H6_CLK_CE		35
    132 #define	H6_CLK_BUS_CE		36
    133 #define	H6_CLK_VE		37
    134 #define	H6_CLK_BUS_VE		38
    135 #define	H6_CLK_EMCE		39
    136 #define	H6_CLK_BUS_EMCE		40
    137 #define	H6_CLK_VP9		41
    138 #define	H6_CLK_BUS_VP9		42
    139 #define	H6_CLK_BUS_DMA		43
    140 #define	H6_CLK_BUS_MSGBOX	44
    141 #define	H6_CLK_BUS_SPINLOCK	45
    142 #define	H6_CLK_BUS_HSTIMER	46
    143 #define	H6_CLK_AVS		47
    144 #define	H6_CLK_BUS_DBG		48
    145 #define	H6_CLK_BUS_PSI		49
    146 #define	H6_CLK_BUS_PWM		50
    147 #define	H6_CLK_BUS_IOMMU	51
    148 #define	H6_CLK_DRAM		52
    149 #define	H6_CLK_MBUS_DMA		53
    150 #define	H6_CLK_MBUS_VE		54
    151 #define	H6_CLK_MBUS_CE		55
    152 #define	H6_CLK_MBUS_TS		56
    153 #define	H6_CLK_MBUS_NAND	57
    154 #define	H6_CLK_MBUS_CSI		58
    155 #define	H6_CLK_MBUS_DEINTERLACE	59
    156 #define	H6_CLK_BUS_DRAM		60
    157 #define	H6_CLK_NAND0		61
    158 #define	H6_CLK_NAND1		62
    159 #define	H6_CLK_BUS_NAND		63
    160 #define	H6_CLK_MMC0		64
    161 #define	H6_CLK_MMC1		65
    162 #define	H6_CLK_MMC2		66
    163 #define	H6_CLK_BUS_MMC0		67
    164 #define	H6_CLK_BUS_MMC1		68
    165 #define	H6_CLK_BUS_MMC2		69
    166 #define	H6_CLK_BUS_UART0	70
    167 #define	H6_CLK_BUS_UART1	71
    168 #define	H6_CLK_BUS_UART2	72
    169 #define	H6_CLK_BUS_UART3	73
    170 #define	H6_CLK_BUS_I2C0		74
    171 #define	H6_CLK_BUS_I2C1		75
    172 #define	H6_CLK_BUS_I2C2		76
    173 #define	H6_CLK_BUS_I2C3		77
    174 #define	H6_CLK_BUS_SCR0		78
    175 #define	H6_CLK_BUS_SCR1		79
    176 #define	H6_CLK_SPI0		80
    177 #define	H6_CLK_SPI1		81
    178 #define	H6_CLK_BUS_SPI0		82
    179 #define	H6_CLK_BUS_SPI1		83
    180 #define	H6_CLK_BUS_EMAC		84
    181 #define	H6_CLK_TS		85
    182 #define	H6_CLK_BUS_TS		86
    183 #define	H6_CLK_IR_TX		87
    184 #define	H6_CLK_BUS_IR_TX	88
    185 #define	H6_CLK_BUS_THS		89
    186 #define	H6_CLK_I2S3		90
    187 #define	H6_CLK_I2S0		91
    188 #define	H6_CLK_I2S1		92
    189 #define	H6_CLK_I2S2		93
    190 #define	H6_CLK_BUS_I2S0		94
    191 #define	H6_CLK_BUS_I2S1		95
    192 #define	H6_CLK_BUS_I2S2		96
    193 #define	H6_CLK_BUS_I2S3		97
    194 #define	H6_CLK_SPDIF		98
    195 #define	H6_CLK_BUS_SPDIF	99
    196 #define	H6_CLK_DMIC		100
    197 #define	H6_CLK_BUS_DMIC		101
    198 #define	H6_CLK_AUDIO_HUB	102
    199 #define	H6_CLK_BUS_AUDIO_HUB	103
    200 #define	H6_CLK_USB_OHCI0	104
    201 #define	H6_CLK_USB_PHY0		105
    202 #define	H6_CLK_USB_PHY1		106
    203 #define	H6_CLK_USB_OHCI3	107
    204 #define	H6_CLK_USB_PHY3		108
    205 #define	H6_CLK_USB_HSIC_12M	109
    206 #define	H6_CLK_USB_HSIC		110
    207 #define	H6_CLK_BUS_OHCI0	111
    208 #define	H6_CLK_BUS_OHCI3	112
    209 #define	H6_CLK_BUS_EHCI0	113
    210 #define	H6_CLK_BUS_XHCI		114
    211 #define	H6_CLK_BUS_EHCI3	115
    212 #define	H6_CLK_BUS_OTG		116
    213 #define	H6_CLK_PCIE_REF_100M	117
    214 #define	H6_CLK_PCIE_REF		118
    215 #define	H6_CLK_PCIE_REF_OUT	119
    216 #define	H6_CLK_PCIE_MAXI	120
    217 #define	H6_CLK_PCIE_AUX		121
    218 #define	H6_CLK_BUS_PCIE		122
    219 #define	H6_CLK_HDMI		123
    220 #define	H6_CLK_HDMI_SLOW	124
    221 #define	H6_CLK_HDMI_CEC		125
    222 #define	H6_CLK_BUS_HDMI		126
    223 #define	H6_CLK_BUS_TCON_TOP	127
    224 #define	H6_CLK_TCON_LCD0	128
    225 #define	H6_CLK_BUS_TCON_LCD0	129
    226 #define	H6_CLK_TCON_TV0		130
    227 #define	H6_CLK_BUS_TCON_TV0	131
    228 #define	H6_CLK_CSI_CCI		132
    229 #define	H6_CLK_CSI_TOP		133
    230 #define	H6_CLK_CSI_MCLK		134
    231 #define	H6_CLK_BUS_CSI		135
    232 #define	H6_CLK_HDCP		136
    233 #define	H6_CLK_BUS_HDCP		137
    234 
    235 #endif /* !_SUN50I_H6_CCU_H */
    236