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    Searched defs:HHI_GCLK_MPEG0 (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/arch/arm/amlogic/
mesongxbb_clkc.c 45 #define HHI_GCLK_MPEG0 CBUS_REG(0x50)
204 MESON_CLK_GATE(MESONGXBB_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9),
205 MESON_CLK_GATE(MESONGXBB_CLOCK_SAR_ADC, "sar_adc", "clk81", HHI_GCLK_MPEG0, 10),
206 MESON_CLK_GATE(MESONGXBB_CLOCK_RNG0, "rng0", "clk81", HHI_GCLK_MPEG0, 12),
207 MESON_CLK_GATE(MESONGXBB_CLOCK_UART0, "uart0", "clk81", HHI_GCLK_MPEG0, 13),
208 MESON_CLK_GATE(MESONGXBB_CLOCK_SDHC, "sdhc", "clk81", HHI_GCLK_MPEG0, 14),
209 MESON_CLK_GATE(MESONGXBB_CLOCK_SDIO, "sdio", "clk81", HHI_GCLK_MPEG0, 17),
210 MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_A, "sd_emmc_a", "clk81", HHI_GCLK_MPEG0, 24),
211 MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_B, "sd_emmc_b", "clk81", HHI_GCLK_MPEG0, 25),
212 MESON_CLK_GATE(MESONGXBB_CLOCK_SD_EMMC_C, "sd_emmc_c", "clk81", HHI_GCLK_MPEG0, 26)
    [all...]
meson8b_clkc.c 51 #define HHI_GCLK_MPEG0 CBUS_REG(0x50)
305 MESON_CLK_GATE(MESON8B_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9),
306 MESON_CLK_GATE(MESON8B_CLOCK_SAR_ADC, "sar_adc", "clk81", HHI_GCLK_MPEG0, 10),
307 MESON_CLK_GATE(MESON8B_CLOCK_RNG0, "rng0", "clk81", HHI_GCLK_MPEG0, 12),
308 MESON_CLK_GATE(MESON8B_CLOCK_UART0, "uart0", "clk81", HHI_GCLK_MPEG0, 13),
309 MESON_CLK_GATE(MESON8B_CLOCK_SDHC, "sdhc", "clk81", HHI_GCLK_MPEG0, 14),
310 MESON_CLK_GATE(MESON8B_CLOCK_SDIO, "sdio", "clk81", HHI_GCLK_MPEG0, 17),
mesong12_clkc.c 121 #define HHI_GCLK_MPEG0 CBUS_REG(0x50)
431 HHI_GCLK_MPEG0, /* reg */ \
436 HHI_GCLK_MPEG0, /* reg */ \
441 HHI_GCLK_MPEG0, /* reg */ \
446 HHI_GCLK_MPEG0, /* reg */ \
451 HHI_GCLK_MPEG0, /* reg */ \
456 HHI_GCLK_MPEG0, /* reg */ \
461 HHI_GCLK_MPEG0, /* reg */ \
466 HHI_GCLK_MPEG0, /* reg */ \
471 HHI_GCLK_MPEG0, /* reg */
    [all...]

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