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    Searched defs:Half (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/tools/llvm-reduce/deltas/
Delta.cpp 66 /// Splits Chunks in half and prints them.
77 int Half = (C.Begin + C.End) / 2;
78 NewChunks.push_back({C.Begin, Half});
79 NewChunks.push_back({Half + 1, C.End});
  /src/external/apache2/llvm/dist/clang/include/clang/AST/
PrettyPrinter.h 73 PolishForDeclaration(false), Half(LO.Half),
227 /// When true, print the half-precision floating-point type as 'half'
229 unsigned Half : 1;
  /src/external/apache2/llvm/dist/clang/lib/Lex/
PreprocessingRecord.cpp 216 size_t Half;
226 Half = Count/2;
228 std::advance(I, Half);
233 Count = Count - Half - 1;
235 Count = Half;
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
Intrinsics.h 120 Half,
  /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/PDB/Native/
SymbolCache.cpp 401 size_t Half;
404 Half = Count / 2;
405 It += Half;
416 Count -= Half + 1;
418 Count = Half;
  /src/external/apache2/llvm/dist/llvm/bindings/ocaml/llvm/
llvm.ml 30 | Half
  /src/external/gpl3/gcc/dist/contrib/
paranoia.cc 86 F2 Half O8 Eight Y
956 FLOAT Half;
1042 Half = "0x1p-1";
1081 TstCond (Failure, Half + MinusOne + Half == Zero, "1/2 + (-1) + 1/2 != 0");
1157 F6 = Half - Third;
1167 Y = Half * U2 + ThirtyTwo * U2 * U2;
1175 F6 = X - Half;
1177 X = Third - Half;
1186 Y = Half * U1 + ThirtyTwo * U1 * U1
    [all...]
  /src/external/gpl3/gcc.old/dist/contrib/
paranoia.cc 86 F2 Half O8 Eight Y
956 FLOAT Half;
1042 Half = "0x1p-1";
1081 TstCond (Failure, Half + MinusOne + Half == Zero, "1/2 + (-1) + 1/2 != 0");
1157 F6 = Half - Third;
1167 Y = Half * U2 + ThirtyTwo * U2 * U2;
1175 F6 = X - Half;
1177 X = Third - Half;
1186 Y = Half * U1 + ThirtyTwo * U1 * U1
    [all...]
  /src/external/apache2/llvm/dist/clang/lib/Serialization/
ASTReader.cpp 6119 size_t Half;
6132 Half = Count / 2;
6134 std::advance(PPI, Half);
6139 Count = Count - Half - 1;
6141 Count = Half;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 2163 // Extract the upper half, since this is where we will find the sign and
2255 const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
2262 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2383 // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 4458 // Ignore the input type. We can only go to exactly half the size of the
4845 // Take only high half of registers if this is high mul.
4866 // half to at least 16-bits, so just handle the one case.
6109 auto Half = MIRBuilder.buildFConstant(Ty, 0.5);
6112 auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 874 // Vector add and sub nodes may conceal a high-half opportunity.
8307 // The extraction can just take the second half
8313 // The extraction can just take the first half
8650 unsigned Half = VT.getVectorNumElements() / 2;
8654 for (unsigned i = 0; i != Half; ++i) {
8655 int MIdx = M[i + j * Half];
8811 // VREV divides the vector in half and swaps within the half.
10186 // Ensure the subvector is half the size of the main vector.
11016 // All 32-bit GPR operations implicitly zero the high-half of the correspondin
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 701 // The half <-> float conversion functions are always soft-float on
1587 // When NEON is used for SP, only half of the register file is available
2120 // Handle f64 or half of a v2f64.
2997 // Half-precision return values can be returned like this:
3047 // Extract the first half and return it in two registers.
3048 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3051 DAG.getVTList(MVT::i32, MVT::i32), Half);
3066 // Extract the 2nd half and fall through to handle it as an f64 value.
6999 // want to check the low half and high half of the shuffle mask as if it wer
    [all...]

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