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  /src/external/gpl3/gdb/dist/sim/testsuite/bfin/
f221.s 25 I3 = 0xfe10 (Z);
26 I3.H = 0x20a9;
31 // R4 = R4 >> 25 || W [ I3 ++ ] = R0.H || R4 = [ I3 ];
c_progctrl_nop.s 24 I3 = 0x7788 (Z);
26 R3 = I3;
issue205.s 9 I0 = 0 (X); I1 = 0 (X); I2 = 0 (X); I3 = 0 (X);
29 I3 = P4;
c_ldimmhalf_lz_ibml.s 16 I3 = 0x2007 (Z);
26 R3 = I3;
43 I3 = 0x3333 (Z);
51 R3 = I3;
68 I3 = 0xbccc (Z);
76 R3 = I3;
c_ldimmhalf_lzhi_ibml.s 19 I3 = 0x2007 (Z);
20 I3.H = 0x2006;
34 R3 = I3;
54 I3 = 0x3333 (Z);
55 I3.H = 0x3000;
67 R3 = I3;
87 I3 = 0xbccc (Z);
88 I3.H = 0xb000;
100 R3 = I3;
c_regmv_dr_imlb.s 20 I3 = R0;
29 R3 = I3;
54 I3 = R1;
62 R3 = I3;
87 I3 = R2;
95 R3 = I3;
120 I3 = R3;
128 R3 = I3;
153 I3 = R4;
161 R3 = I3;
    [all...]
c_regmv_pr_imlb.s 21 I3 = P1;
29 R3 = I3;
47 I3 = P2;
55 R3 = I3;
73 I3 = P3;
81 R3 = I3;
99 I3 = P4;
107 R3 = I3;
125 I3 = P5;
133 R3 = I3;
    [all...]
disalnexcpt_implicit.S 12 # Set up I0/I1/I2/I3 to be unaligned by 0/1/2/3 bytes
30 I3 = R3;
viterbi2.s 111 I3 = P5; // I3 points to APM[To]
138 R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L || R3.H = W [ I2 ++ ] || [ I3 ++ ] = R6;
146 [ I3 ++ ] = R6;
c_ldimmhalf_pibml.s 65 I3 = 0x3456 (X);
73 R3 = I3;
90 I3 = -3456 (X);
98 R3 = I3;
115 I3 = 0x7d56 (X);
123 R3 = I3;
c_regmv_dag_lz_dep.s 32 I3 = R3;
33 I3 = 0x7788 (Z);
34 R3 = I3;
c_regmv_dr_dep_nostall.s 53 I3 = R3;
75 R4 = I3;
90 imm32 i3, 0x66667777;
103 R3 = I3;
125 imm32 i3, 0x16661777;
138 R3 = I3;
192 I3 = R3;
206 R4 = I3;
c_regmv_imlb_dep_nostall.s 23 I3 = P3;
24 R3 = I3;
46 R4 = I3;
123 I3 = P3;
124 L3 = I3;
154 R4 = I3;
182 I3 = L3;
199 R7 = I3;
228 imm32 i3, 0x01637772;
239 M3 = I3;
    [all...]
c_regmv_imlb_dep_stall.s 23 I3 = R3;
24 R2 = I3;
47 R4 = I3;
64 imm32 i3, 0x16617741;
83 I3 = R7;
84 FP = I3;
101 R7 = I3;
230 I3 = R3;
231 L3 = I3;
262 R4 = I3;
    [all...]
c_regmv_imlb_imlb.s 12 imm32 i3, 0x44444444;
31 I3 = I3;
39 I2 = I3;
40 I3 = I0;
49 R3 = I3;
65 I1 = I3;
67 I3 = I1;
76 R3 = I3;
91 I0 = I3;
    [all...]
c_regmv_pr_dep_nostall.s 44 I3 = FP;
46 R4 = I3;
141 imm32 i3, 0x63667737;
154 P4 = I3;
177 imm32 i3, 0x12661777;
190 P3 = I3;
244 I3 = P3;
258 R4 = I3;
  /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
f221.s 25 I3 = 0xfe10 (Z);
26 I3.H = 0x20a9;
31 // R4 = R4 >> 25 || W [ I3 ++ ] = R0.H || R4 = [ I3 ];
c_progctrl_nop.s 24 I3 = 0x7788 (Z);
26 R3 = I3;
issue205.s 9 I0 = 0 (X); I1 = 0 (X); I2 = 0 (X); I3 = 0 (X);
29 I3 = P4;
c_ldimmhalf_lz_ibml.s 16 I3 = 0x2007 (Z);
26 R3 = I3;
43 I3 = 0x3333 (Z);
51 R3 = I3;
68 I3 = 0xbccc (Z);
76 R3 = I3;
c_ldimmhalf_lzhi_ibml.s 19 I3 = 0x2007 (Z);
20 I3.H = 0x2006;
34 R3 = I3;
54 I3 = 0x3333 (Z);
55 I3.H = 0x3000;
67 R3 = I3;
87 I3 = 0xbccc (Z);
88 I3.H = 0xb000;
100 R3 = I3;
c_regmv_dr_imlb.s 20 I3 = R0;
29 R3 = I3;
54 I3 = R1;
62 R3 = I3;
87 I3 = R2;
95 R3 = I3;
120 I3 = R3;
128 R3 = I3;
153 I3 = R4;
161 R3 = I3;
    [all...]
c_regmv_pr_imlb.s 21 I3 = P1;
29 R3 = I3;
47 I3 = P2;
55 R3 = I3;
73 I3 = P3;
81 R3 = I3;
99 I3 = P4;
107 R3 = I3;
125 I3 = P5;
133 R3 = I3;
    [all...]
disalnexcpt_implicit.S 12 # Set up I0/I1/I2/I3 to be unaligned by 0/1/2/3 bytes
30 I3 = R3;
viterbi2.s 111 I3 = P5; // I3 points to APM[To]
138 R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L || R3.H = W [ I2 ++ ] || [ I3 ++ ] = R6;
146 [ I3 ++ ] = R6;

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