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    Searched defs:IMM5 (Results 1 - 17 of 17) sorted by relevancy

  /src/external/gpl3/binutils/dist/opcodes/
d30v-opc.c 364 #define IMM5 (Ab + 1)
366 #define IMM5U (IMM5 + 1)
457 { SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */
459 { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */
470 { SHORT_MODINC, 1, { Rb2, IMM5 } }, /* Rb2,imm5 (modinc) */
471 { SHORT_MODDEC, 3, { Rb2, IMM5 } }, /* Rb2,imm5 (moddec) */
v850-opc.c 1115 /* The imm5 field in a format 2 insn. */
1119 /* The imm5 field in a format 11 insn. */
1129 /* The unsigned imm5 field in a format 2 insn. */
1133 /* The imm5 field in a prepare/dispose instruction. */
1134 #define IMM5 (I5U + 1)
1138 #define D5_4U (IMM5 + 1)
1476 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 },
1477 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 },
1659 { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 },
1660 { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 }
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
d30v-opc.c 364 #define IMM5 (Ab + 1)
366 #define IMM5U (IMM5 + 1)
457 { SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */
459 { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */
470 { SHORT_MODINC, 1, { Rb2, IMM5 } }, /* Rb2,imm5 (modinc) */
471 { SHORT_MODDEC, 3, { Rb2, IMM5 } }, /* Rb2,imm5 (moddec) */
v850-opc.c 1115 /* The imm5 field in a format 2 insn. */
1119 /* The imm5 field in a format 11 insn. */
1129 /* The unsigned imm5 field in a format 2 insn. */
1133 /* The imm5 field in a prepare/dispose instruction. */
1134 #define IMM5 (I5U + 1)
1138 #define D5_4U (IMM5 + 1)
1476 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 },
1477 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 },
1659 { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 },
1660 { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 }
    [all...]
  /src/external/gpl3/gdb/dist/opcodes/
d30v-opc.c 364 #define IMM5 (Ab + 1)
366 #define IMM5U (IMM5 + 1)
457 { SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */
459 { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */
470 { SHORT_MODINC, 1, { Rb2, IMM5 } }, /* Rb2,imm5 (modinc) */
471 { SHORT_MODDEC, 3, { Rb2, IMM5 } }, /* Rb2,imm5 (moddec) */
v850-opc.c 1115 /* The imm5 field in a format 2 insn. */
1119 /* The imm5 field in a format 11 insn. */
1129 /* The unsigned imm5 field in a format 2 insn. */
1133 /* The imm5 field in a prepare/dispose instruction. */
1134 #define IMM5 (I5U + 1)
1138 #define D5_4U (IMM5 + 1)
1476 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 },
1477 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 },
1659 { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 },
1660 { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 }
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
d30v-opc.c 364 #define IMM5 (Ab + 1)
366 #define IMM5U (IMM5 + 1)
457 { SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */
459 { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */
470 { SHORT_MODINC, 1, { Rb2, IMM5 } }, /* Rb2,imm5 (modinc) */
471 { SHORT_MODDEC, 3, { Rb2, IMM5 } }, /* Rb2,imm5 (moddec) */
v850-opc.c 1115 /* The imm5 field in a format 2 insn. */
1119 /* The imm5 field in a format 11 insn. */
1129 /* The unsigned imm5 field in a format 2 insn. */
1133 /* The imm5 field in a prepare/dispose instruction. */
1134 #define IMM5 (I5U + 1)
1138 #define D5_4U (IMM5 + 1)
1476 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 },
1477 { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 },
1659 { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 },
1660 { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 }
    [all...]
  /src/external/gpl3/gdb/dist/sim/mcore/
interp.c 280 #define IMM5 ((inst >> 4) & 0x1F)
780 r = IMM5;
820 r = IMM5;
863 gr[RD] + (IMM5 + 1);
867 int tmp = (IMM5 + 1);
880 gr[RD] - (IMM5 + 1);
887 IMM5 - gr[RD];
890 if (gr[RD] != IMM5)
902 unsigned imm = IMM5;
950 gr[RD] = gr[RD] & IMM5;
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/mcore/
interp.c 280 #define IMM5 ((inst >> 4) & 0x1F)
780 r = IMM5;
820 r = IMM5;
863 gr[RD] + (IMM5 + 1);
867 int tmp = (IMM5 + 1);
880 gr[RD] - (IMM5 + 1);
887 IMM5 - gr[RD];
890 if (gr[RD] != IMM5)
902 unsigned imm = IMM5;
950 gr[RD] = gr[RD] & IMM5;
    [all...]
  /src/sys/external/bsd/sljit/dist/sljit_src/
sljitNativeARM_T2_32.c 77 #define IMM5(imm) \
659 return push_inst32(compiler, LSL_WI | (flags & SET_FLAGS) | RD4(dst) | RM4(reg) | IMM5(imm));
663 return push_inst32(compiler, LSR_WI | (flags & SET_FLAGS) | RD4(dst) | RM4(reg) | IMM5(imm));
667 return push_inst32(compiler, ASR_WI | (flags & SET_FLAGS) | RD4(dst) | RM4(reg) | IMM5(imm));
842 /* w u l */ 0x6800 /* ldr imm5 */,
843 /* w u s */ 0x6000 /* str imm5 */,
844 /* w s l */ 0x6800 /* ldr imm5 */,
845 /* w s s */ 0x6000 /* str imm5 */,
847 /* b u l */ 0x7800 /* ldrb imm5 */,
848 /* b u s */ 0x7000 /* strb imm5 */,
    [all...]
  /src/external/gpl3/gcc/dist/gcc/config/epiphany/
epiphany.h 419 #define IMM5(X) (IN_RANGE ((X), 0, 0x1F))
  /src/external/gpl3/gcc.old/dist/gcc/config/epiphany/
epiphany.h 421 #define IMM5(X) (IN_RANGE ((X), 0, 0x1F))
  /src/external/gpl3/binutils/dist/include/opcode/
h8300.h 123 IMM5 = IMM | L_5,
1751 {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8, E}}},
1760 {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}},
1770 {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}},
1778 {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8, E}}},
1787 {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}}
    [all...]
  /src/external/gpl3/binutils.old/dist/include/opcode/
h8300.h 123 IMM5 = IMM | L_5,
1751 {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8, E}}},
1760 {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}},
1770 {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}},
1778 {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8, E}}},
1787 {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}}
    [all...]
  /src/external/gpl3/gdb/dist/include/opcode/
h8300.h 123 IMM5 = IMM | L_5,
1751 {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8, E}}},
1760 {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}},
1770 {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}},
1778 {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8, E}}},
1787 {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}}
    [all...]
  /src/external/gpl3/gdb.old/dist/include/opcode/
h8300.h 123 IMM5 = IMM | L_5,
1751 {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8, E}}},
1760 {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}},
1770 {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}},
1778 {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8, E}}},
1787 {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}}
    [all...]

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