1 /* $NetBSD: imx8mm-clock.h,v 1.1.1.3 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright 2017-2018 NXP 6 */ 7 8 #ifndef __DT_BINDINGS_CLOCK_IMX8MM_H 9 #define __DT_BINDINGS_CLOCK_IMX8MM_H 10 11 #define IMX8MM_CLK_DUMMY 0 12 #define IMX8MM_CLK_32K 1 13 #define IMX8MM_CLK_24M 2 14 #define IMX8MM_OSC_HDMI_CLK 3 15 #define IMX8MM_CLK_EXT1 4 16 #define IMX8MM_CLK_EXT2 5 17 #define IMX8MM_CLK_EXT3 6 18 #define IMX8MM_CLK_EXT4 7 19 #define IMX8MM_AUDIO_PLL1_REF_SEL 8 20 #define IMX8MM_AUDIO_PLL2_REF_SEL 9 21 #define IMX8MM_VIDEO_PLL1_REF_SEL 10 22 #define IMX8MM_DRAM_PLL_REF_SEL 11 23 #define IMX8MM_GPU_PLL_REF_SEL 12 24 #define IMX8MM_VPU_PLL_REF_SEL 13 25 #define IMX8MM_ARM_PLL_REF_SEL 14 26 #define IMX8MM_SYS_PLL1_REF_SEL 15 27 #define IMX8MM_SYS_PLL2_REF_SEL 16 28 #define IMX8MM_SYS_PLL3_REF_SEL 17 29 #define IMX8MM_AUDIO_PLL1 18 30 #define IMX8MM_AUDIO_PLL2 19 31 #define IMX8MM_VIDEO_PLL1 20 32 #define IMX8MM_DRAM_PLL 21 33 #define IMX8MM_GPU_PLL 22 34 #define IMX8MM_VPU_PLL 23 35 #define IMX8MM_ARM_PLL 24 36 #define IMX8MM_SYS_PLL1 25 37 #define IMX8MM_SYS_PLL2 26 38 #define IMX8MM_SYS_PLL3 27 39 #define IMX8MM_AUDIO_PLL1_BYPASS 28 40 #define IMX8MM_AUDIO_PLL2_BYPASS 29 41 #define IMX8MM_VIDEO_PLL1_BYPASS 30 42 #define IMX8MM_DRAM_PLL_BYPASS 31 43 #define IMX8MM_GPU_PLL_BYPASS 32 44 #define IMX8MM_VPU_PLL_BYPASS 33 45 #define IMX8MM_ARM_PLL_BYPASS 34 46 #define IMX8MM_SYS_PLL1_BYPASS 35 47 #define IMX8MM_SYS_PLL2_BYPASS 36 48 #define IMX8MM_SYS_PLL3_BYPASS 37 49 #define IMX8MM_AUDIO_PLL1_OUT 38 50 #define IMX8MM_AUDIO_PLL2_OUT 39 51 #define IMX8MM_VIDEO_PLL1_OUT 40 52 #define IMX8MM_DRAM_PLL_OUT 41 53 #define IMX8MM_GPU_PLL_OUT 42 54 #define IMX8MM_VPU_PLL_OUT 43 55 #define IMX8MM_ARM_PLL_OUT 44 56 #define IMX8MM_SYS_PLL1_OUT 45 57 #define IMX8MM_SYS_PLL2_OUT 46 58 #define IMX8MM_SYS_PLL3_OUT 47 59 #define IMX8MM_SYS_PLL1_40M 48 60 #define IMX8MM_SYS_PLL1_80M 49 61 #define IMX8MM_SYS_PLL1_100M 50 62 #define IMX8MM_SYS_PLL1_133M 51 63 #define IMX8MM_SYS_PLL1_160M 52 64 #define IMX8MM_SYS_PLL1_200M 53 65 #define IMX8MM_SYS_PLL1_266M 54 66 #define IMX8MM_SYS_PLL1_400M 55 67 #define IMX8MM_SYS_PLL1_800M 56 68 #define IMX8MM_SYS_PLL2_50M 57 69 #define IMX8MM_SYS_PLL2_100M 58 70 #define IMX8MM_SYS_PLL2_125M 59 71 #define IMX8MM_SYS_PLL2_166M 60 72 #define IMX8MM_SYS_PLL2_200M 61 73 #define IMX8MM_SYS_PLL2_250M 62 74 #define IMX8MM_SYS_PLL2_333M 63 75 #define IMX8MM_SYS_PLL2_500M 64 76 #define IMX8MM_SYS_PLL2_1000M 65 77 78 /* core */ 79 #define IMX8MM_CLK_A53_SRC 66 80 #define IMX8MM_CLK_M4_SRC 67 81 #define IMX8MM_CLK_VPU_SRC 68 82 #define IMX8MM_CLK_GPU3D_SRC 69 83 #define IMX8MM_CLK_GPU2D_SRC 70 84 #define IMX8MM_CLK_A53_CG 71 85 #define IMX8MM_CLK_M4_CG 72 86 #define IMX8MM_CLK_VPU_CG 73 87 #define IMX8MM_CLK_GPU3D_CG 74 88 #define IMX8MM_CLK_GPU2D_CG 75 89 #define IMX8MM_CLK_A53_DIV 76 90 #define IMX8MM_CLK_M4_DIV 77 91 #define IMX8MM_CLK_VPU_DIV 78 92 #define IMX8MM_CLK_GPU3D_DIV 79 93 #define IMX8MM_CLK_GPU2D_DIV 80 94 95 /* bus */ 96 #define IMX8MM_CLK_MAIN_AXI 81 97 #define IMX8MM_CLK_ENET_AXI 82 98 #define IMX8MM_CLK_NAND_USDHC_BUS 83 99 #define IMX8MM_CLK_VPU_BUS 84 100 #define IMX8MM_CLK_DISP_AXI 85 101 #define IMX8MM_CLK_DISP_APB 86 102 #define IMX8MM_CLK_DISP_RTRM 87 103 #define IMX8MM_CLK_USB_BUS 88 104 #define IMX8MM_CLK_GPU_AXI 89 105 #define IMX8MM_CLK_GPU_AHB 90 106 #define IMX8MM_CLK_NOC 91 107 #define IMX8MM_CLK_NOC_APB 92 108 109 #define IMX8MM_CLK_AHB 93 110 #define IMX8MM_CLK_AUDIO_AHB 94 111 #define IMX8MM_CLK_IPG_ROOT 95 112 #define IMX8MM_CLK_IPG_AUDIO_ROOT 96 113 114 #define IMX8MM_CLK_DRAM_ALT 97 115 #define IMX8MM_CLK_DRAM_APB 98 116 #define IMX8MM_CLK_VPU_G1 99 117 #define IMX8MM_CLK_VPU_G2 100 118 #define IMX8MM_CLK_DISP_DTRC 101 119 #define IMX8MM_CLK_DISP_DC8000 102 120 #define IMX8MM_CLK_PCIE1_CTRL 103 121 #define IMX8MM_CLK_PCIE1_PHY 104 122 #define IMX8MM_CLK_PCIE1_AUX 105 123 #define IMX8MM_CLK_DC_PIXEL 106 124 #define IMX8MM_CLK_LCDIF_PIXEL 107 125 #define IMX8MM_CLK_SAI1 108 126 #define IMX8MM_CLK_SAI2 109 127 #define IMX8MM_CLK_SAI3 110 128 #define IMX8MM_CLK_SAI4 111 129 #define IMX8MM_CLK_SAI5 112 130 #define IMX8MM_CLK_SAI6 113 131 #define IMX8MM_CLK_SPDIF1 114 132 #define IMX8MM_CLK_SPDIF2 115 133 #define IMX8MM_CLK_ENET_REF 116 134 #define IMX8MM_CLK_ENET_TIMER 117 135 #define IMX8MM_CLK_ENET_PHY_REF 118 136 #define IMX8MM_CLK_NAND 119 137 #define IMX8MM_CLK_QSPI 120 138 #define IMX8MM_CLK_USDHC1 121 139 #define IMX8MM_CLK_USDHC2 122 140 #define IMX8MM_CLK_I2C1 123 141 #define IMX8MM_CLK_I2C2 124 142 #define IMX8MM_CLK_I2C3 125 143 #define IMX8MM_CLK_I2C4 126 144 #define IMX8MM_CLK_UART1 127 145 #define IMX8MM_CLK_UART2 128 146 #define IMX8MM_CLK_UART3 129 147 #define IMX8MM_CLK_UART4 130 148 #define IMX8MM_CLK_USB_CORE_REF 131 149 #define IMX8MM_CLK_USB_PHY_REF 132 150 #define IMX8MM_CLK_ECSPI1 133 151 #define IMX8MM_CLK_ECSPI2 134 152 #define IMX8MM_CLK_PWM1 135 153 #define IMX8MM_CLK_PWM2 136 154 #define IMX8MM_CLK_PWM3 137 155 #define IMX8MM_CLK_PWM4 138 156 #define IMX8MM_CLK_GPT1 139 157 #define IMX8MM_CLK_WDOG 140 158 #define IMX8MM_CLK_WRCLK 141 159 #define IMX8MM_CLK_DSI_CORE 142 160 #define IMX8MM_CLK_DSI_PHY_REF 143 161 #define IMX8MM_CLK_DSI_DBI 144 162 #define IMX8MM_CLK_USDHC3 145 163 #define IMX8MM_CLK_CSI1_CORE 146 164 #define IMX8MM_CLK_CSI1_PHY_REF 147 165 #define IMX8MM_CLK_CSI1_ESC 148 166 #define IMX8MM_CLK_CSI2_CORE 149 167 #define IMX8MM_CLK_CSI2_PHY_REF 150 168 #define IMX8MM_CLK_CSI2_ESC 151 169 #define IMX8MM_CLK_PCIE2_CTRL 152 170 #define IMX8MM_CLK_PCIE2_PHY 153 171 #define IMX8MM_CLK_PCIE2_AUX 154 172 #define IMX8MM_CLK_ECSPI3 155 173 #define IMX8MM_CLK_PDM 156 174 #define IMX8MM_CLK_VPU_H1 157 175 #define IMX8MM_CLK_CLKO1 158 176 177 #define IMX8MM_CLK_ECSPI1_ROOT 159 178 #define IMX8MM_CLK_ECSPI2_ROOT 160 179 #define IMX8MM_CLK_ECSPI3_ROOT 161 180 #define IMX8MM_CLK_ENET1_ROOT 162 181 #define IMX8MM_CLK_GPT1_ROOT 163 182 #define IMX8MM_CLK_I2C1_ROOT 164 183 #define IMX8MM_CLK_I2C2_ROOT 165 184 #define IMX8MM_CLK_I2C3_ROOT 166 185 #define IMX8MM_CLK_I2C4_ROOT 167 186 #define IMX8MM_CLK_OCOTP_ROOT 168 187 #define IMX8MM_CLK_PCIE1_ROOT 169 188 #define IMX8MM_CLK_PWM1_ROOT 170 189 #define IMX8MM_CLK_PWM2_ROOT 171 190 #define IMX8MM_CLK_PWM3_ROOT 172 191 #define IMX8MM_CLK_PWM4_ROOT 173 192 #define IMX8MM_CLK_QSPI_ROOT 174 193 #define IMX8MM_CLK_NAND_ROOT 175 194 #define IMX8MM_CLK_SAI1_ROOT 176 195 #define IMX8MM_CLK_SAI1_IPG 177 196 #define IMX8MM_CLK_SAI2_ROOT 178 197 #define IMX8MM_CLK_SAI2_IPG 179 198 #define IMX8MM_CLK_SAI3_ROOT 180 199 #define IMX8MM_CLK_SAI3_IPG 181 200 #define IMX8MM_CLK_SAI4_ROOT 182 201 #define IMX8MM_CLK_SAI4_IPG 183 202 #define IMX8MM_CLK_SAI5_ROOT 184 203 #define IMX8MM_CLK_SAI5_IPG 185 204 #define IMX8MM_CLK_SAI6_ROOT 186 205 #define IMX8MM_CLK_SAI6_IPG 187 206 #define IMX8MM_CLK_UART1_ROOT 188 207 #define IMX8MM_CLK_UART2_ROOT 189 208 #define IMX8MM_CLK_UART3_ROOT 190 209 #define IMX8MM_CLK_UART4_ROOT 191 210 #define IMX8MM_CLK_USB1_CTRL_ROOT 192 211 #define IMX8MM_CLK_GPU3D_ROOT 193 212 #define IMX8MM_CLK_USDHC1_ROOT 194 213 #define IMX8MM_CLK_USDHC2_ROOT 195 214 #define IMX8MM_CLK_WDOG1_ROOT 196 215 #define IMX8MM_CLK_WDOG2_ROOT 197 216 #define IMX8MM_CLK_WDOG3_ROOT 198 217 #define IMX8MM_CLK_VPU_G1_ROOT 199 218 #define IMX8MM_CLK_GPU_BUS_ROOT 200 219 #define IMX8MM_CLK_VPU_H1_ROOT 201 220 #define IMX8MM_CLK_VPU_G2_ROOT 202 221 #define IMX8MM_CLK_PDM_ROOT 203 222 #define IMX8MM_CLK_DISP_ROOT 204 223 #define IMX8MM_CLK_DISP_AXI_ROOT 205 224 #define IMX8MM_CLK_DISP_APB_ROOT 206 225 #define IMX8MM_CLK_DISP_RTRM_ROOT 207 226 #define IMX8MM_CLK_USDHC3_ROOT 208 227 #define IMX8MM_CLK_TMU_ROOT 209 228 #define IMX8MM_CLK_VPU_DEC_ROOT 210 229 #define IMX8MM_CLK_SDMA1_ROOT 211 230 #define IMX8MM_CLK_SDMA2_ROOT 212 231 #define IMX8MM_CLK_SDMA3_ROOT 213 232 #define IMX8MM_CLK_GPT_3M 214 233 #define IMX8MM_CLK_ARM 215 234 #define IMX8MM_CLK_PDM_IPG 216 235 #define IMX8MM_CLK_GPU2D_ROOT 217 236 #define IMX8MM_CLK_MU_ROOT 218 237 #define IMX8MM_CLK_CSI1_ROOT 219 238 239 #define IMX8MM_CLK_DRAM_CORE 220 240 #define IMX8MM_CLK_DRAM_ALT_ROOT 221 241 242 #define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 243 244 #define IMX8MM_CLK_GPIO1_ROOT 223 245 #define IMX8MM_CLK_GPIO2_ROOT 224 246 #define IMX8MM_CLK_GPIO3_ROOT 225 247 #define IMX8MM_CLK_GPIO4_ROOT 226 248 #define IMX8MM_CLK_GPIO5_ROOT 227 249 250 #define IMX8MM_CLK_SNVS_ROOT 228 251 #define IMX8MM_CLK_GIC 229 252 253 #define IMX8MM_SYS_PLL1_40M_CG 230 254 #define IMX8MM_SYS_PLL1_80M_CG 231 255 #define IMX8MM_SYS_PLL1_100M_CG 232 256 #define IMX8MM_SYS_PLL1_133M_CG 233 257 #define IMX8MM_SYS_PLL1_160M_CG 234 258 #define IMX8MM_SYS_PLL1_200M_CG 235 259 #define IMX8MM_SYS_PLL1_266M_CG 236 260 #define IMX8MM_SYS_PLL1_400M_CG 237 261 #define IMX8MM_SYS_PLL2_50M_CG 238 262 #define IMX8MM_SYS_PLL2_100M_CG 239 263 #define IMX8MM_SYS_PLL2_125M_CG 240 264 #define IMX8MM_SYS_PLL2_166M_CG 241 265 #define IMX8MM_SYS_PLL2_200M_CG 242 266 #define IMX8MM_SYS_PLL2_250M_CG 243 267 #define IMX8MM_SYS_PLL2_333M_CG 244 268 #define IMX8MM_SYS_PLL2_500M_CG 245 269 270 #define IMX8MM_CLK_M4_CORE 246 271 #define IMX8MM_CLK_VPU_CORE 247 272 #define IMX8MM_CLK_GPU3D_CORE 248 273 #define IMX8MM_CLK_GPU2D_CORE 249 274 275 #define IMX8MM_CLK_CLKO2 250 276 277 #define IMX8MM_CLK_A53_CORE 251 278 279 #define IMX8MM_CLK_CLKOUT1_SEL 252 280 #define IMX8MM_CLK_CLKOUT1_DIV 253 281 #define IMX8MM_CLK_CLKOUT1 254 282 #define IMX8MM_CLK_CLKOUT2_SEL 255 283 #define IMX8MM_CLK_CLKOUT2_DIV 256 284 #define IMX8MM_CLK_CLKOUT2 257 285 286 287 #define IMX8MM_CLK_END 258 288 289 #endif 290
Indexes created Mon Oct 06 15:09:44 GMT 2025