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      1 /*
      2  * This file was generated automatically from PDF file by mkiomuxreg_imx51.rb
      3  *
      4  */
      5 #ifndef	_IMX51_IOMUXREG_H
      6 #define	_IMX51_IOMUXREG_H
      7 
      8 /* register offset address */
      9 
     10 #define IOMUXC_GPR0					0x0000
     11 #define IOMUXC_GPR1					0x0004
     12 #define IOMUXC_OBSERVE_MUX_0				0x0008
     13 #define IOMUXC_OBSERVE_MUX_1				0x000c
     14 #define IOMUXC_OBSERVE_MUX_2				0x0010
     15 #define IOMUXC_OBSERVE_MUX_3				0x0014
     16 #define IOMUXC_OBSERVE_MUX_4				0x0018
     17 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA0			0x001c
     18 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA1			0x0020
     19 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA2			0x0024
     20 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA3			0x0028
     21 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA4			0x002c
     22 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA5			0x0030
     23 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA6			0x0034
     24 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA7			0x0038
     25 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA8			0x003c
     26 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA9			0x0040
     27 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA10			0x0044
     28 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA11			0x0048
     29 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA12			0x004c
     30 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA13			0x0050
     31 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA14			0x0054
     32 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA15			0x0058
     33 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D16			0x005c
     34 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D17			0x0060
     35 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D18			0x0064
     36 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D19			0x0068
     37 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D20			0x006c
     38 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D21			0x0070
     39 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D22			0x0074
     40 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D23			0x0078
     41 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D24			0x007c
     42 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D25			0x0080
     43 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D26			0x0084
     44 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D27			0x0088
     45 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D28			0x008c
     46 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D29			0x0090
     47 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D30			0x0094
     48 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D31			0x0098
     49 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A16			0x009c
     50 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A17			0x00a0
     51 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A18			0x00a4
     52 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A19			0x00a8
     53 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A20			0x00ac
     54 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A21			0x00b0
     55 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A22			0x00b4
     56 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A23			0x00b8
     57 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A24			0x00bc
     58 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A25			0x00c0
     59 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A26			0x00c4
     60 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A27			0x00c8
     61 #define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0			0x00cc
     62 #define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1			0x00d0
     63 #define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2			0x00d4
     64 #define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3			0x00d8
     65 #define IOMUXC_SW_MUX_CTL_PAD_EIM_OE			0x00dc
     66 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0			0x00e0
     67 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1			0x00e4
     68 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS2			0x00e8
     69 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS3			0x00ec
     70 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS4			0x00f0
     71 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS5			0x00f4
     72 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DTACK			0x00f8
     73 #define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA			0x00fc
     74 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CRE			0x0100
     75 #define IOMUXC_SW_MUX_CTL_PAD_DRAM_CS1			0x0104
     76 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B		0x0108
     77 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B		0x010c
     78 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE			0x0110
     79 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE			0x0114
     80 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B		0x0118
     81 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0			0x011c
     82 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1			0x0120
     83 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2			0x0124
     84 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3			0x0128
     85 #define IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND			0x012c
     86 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0			0x0130
     87 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1			0x0134
     88 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2			0x0138
     89 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3			0x013c
     90 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4			0x0140
     91 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5			0x0144
     92 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6			0x0148
     93 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7			0x014c
     94 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT		0x0150
     95 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D15			0x0154
     96 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D14			0x0158
     97 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D13			0x015c
     98 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D12			0x0160
     99 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D11			0x0164
    100 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D10			0x0168
    101 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D9			0x016c
    102 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D8			0x0170
    103 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7			0x0174
    104 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6			0x0178
    105 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5			0x017c
    106 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4			0x0180
    107 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3			0x0184
    108 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2			0x0188
    109 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1			0x018c
    110 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0			0x0190
    111 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D8			0x0194
    112 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D9			0x0198
    113 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D10			0x019c
    114 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D11			0x01a0
    115 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D12			0x01a4
    116 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D13			0x01a8
    117 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D14			0x01ac
    118 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D15			0x01b0
    119 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D16			0x01b4
    120 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D17			0x01b8
    121 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D18			0x01bc
    122 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D19			0x01c0
    123 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_VSYNC		0x01c4
    124 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_HSYNC		0x01c8
    125 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D12			0x01cc
    126 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D13			0x01d0
    127 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D14			0x01d4
    128 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D15			0x01d8
    129 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D16			0x01dc
    130 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D17			0x01e0
    131 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D18			0x01e4
    132 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D19			0x01e8
    133 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_VSYNC		0x01ec
    134 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_HSYNC		0x01f0
    135 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_PIXCLK		0x01f4
    136 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_CLK			0x01f8
    137 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_DAT			0x01fc
    138 #define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_TXD		0x0200
    139 #define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_RXD		0x0204
    140 #define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_CK		0x0208
    141 #define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_FS		0x020c
    142 #define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MOSI		0x0210
    143 #define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MISO		0x0214
    144 #define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS0			0x0218
    145 #define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS1			0x021c
    146 #define IOMUXC_SW_MUX_CTL_PAD_CSPI1_RDY			0x0220
    147 #define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SCLK		0x0224
    148 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RXD			0x0228
    149 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TXD			0x022c
    150 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS			0x0230
    151 #define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS			0x0234
    152 #define IOMUXC_SW_MUX_CTL_PAD_UART2_RXD			0x0238
    153 #define IOMUXC_SW_MUX_CTL_PAD_UART2_TXD			0x023c
    154 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RXD			0x0240
    155 #define IOMUXC_SW_MUX_CTL_PAD_UART3_TXD			0x0244
    156 #define IOMUXC_SW_MUX_CTL_PAD_OWIRE_LINE		0x0248
    157 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0			0x024c
    158 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1			0x0250
    159 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2			0x0254
    160 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3			0x0258
    161 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0			0x025c
    162 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1			0x0260
    163 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2			0x0264
    164 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3			0x0268
    165 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4			0x026c
    166 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL5			0x0270
    167 #define IOMUXC_SW_MUX_CTL_PAD_JTAG_DE_B			0x0274
    168 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_CLK			0x0278
    169 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DIR			0x027c
    170 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_STP			0x0280
    171 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_NXT			0x0284
    172 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA0		0x0288
    173 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA1		0x028c
    174 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA2		0x0290
    175 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA3		0x0294
    176 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA4		0x0298
    177 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA5		0x029c
    178 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA6		0x02a0
    179 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA7		0x02a4
    180 #define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11			0x02a8
    181 #define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12			0x02ac
    182 #define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13			0x02b0
    183 #define IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS			0x02b4
    184 #define IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS			0x02b8
    185 #define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIN		0x02bc
    186 #define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIO		0x02c0
    187 #define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_CLK		0x02c4
    188 #define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_RS		0x02c8
    189 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0		0x02cc
    190 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1		0x02d0
    191 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2		0x02d4
    192 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3		0x02d8
    193 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4		0x02dc
    194 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5		0x02e0
    195 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6		0x02e4
    196 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7		0x02e8
    197 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8		0x02ec
    198 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9		0x02f0
    199 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10		0x02f4
    200 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT11		0x02f8
    201 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12		0x02fc
    202 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13		0x0300
    203 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14		0x0304
    204 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15		0x0308
    205 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16		0x030c
    206 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17		0x0310
    207 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT18		0x0314
    208 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT19		0x0318
    209 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT20		0x031c
    210 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT21		0x0320
    211 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT22		0x0324
    212 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT23		0x0328
    213 #define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3			0x032c
    214 #define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2			0x0330
    215 #define IOMUXC_SW_MUX_CTL_PAD_DI_GP1			0x0334
    216 #define IOMUXC_SW_MUX_CTL_PAD_DI_GP2			0x0338
    217 #define IOMUXC_SW_MUX_CTL_PAD_DI_GP3			0x033c
    218 #define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN4			0x0340
    219 #define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN2			0x0344
    220 #define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN3			0x0348
    221 #define IOMUXC_SW_MUX_CTL_PAD_DI2_DISP_CLK		0x034c
    222 #define IOMUXC_SW_MUX_CTL_PAD_DI_GP4			0x0350
    223 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT0		0x0354
    224 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT1		0x0358
    225 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT2		0x035c
    226 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT3		0x0360
    227 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT4		0x0364
    228 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT5		0x0368
    229 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT6		0x036c
    230 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT7		0x0370
    231 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT8		0x0374
    232 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT9		0x0378
    233 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT10		0x037c
    234 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT11		0x0380
    235 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT12		0x0384
    236 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT13		0x0388
    237 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT14		0x038c
    238 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT15		0x0390
    239 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD			0x0394
    240 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK			0x0398
    241 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0			0x039c
    242 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1			0x03a0
    243 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2			0x03a4
    244 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3			0x03a8
    245 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_0			0x03ac
    246 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_1			0x03b0
    247 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD			0x03b4
    248 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK			0x03b8
    249 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0			0x03bc
    250 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1			0x03c0
    251 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2			0x03c4
    252 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3			0x03c8
    253 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_2			0x03cc
    254 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_3			0x03d0
    255 #define IOMUXC_SW_MUX_CTL_PAD_PMIC_INT_REQ		0x03d4
    256 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_4			0x03d8
    257 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_5			0x03dc
    258 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_6			0x03e0
    259 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_7			0x03e4
    260 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_8			0x03e8
    261 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_9			0x03ec
    262 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D16			0x03f0
    263 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D17			0x03f4
    264 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D18			0x03f8
    265 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D19			0x03fc
    266 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D20			0x0400
    267 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D21			0x0404
    268 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D22			0x0408
    269 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D23			0x040c
    270 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D24			0x0410
    271 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D25			0x0414
    272 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D26			0x0418
    273 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D27			0x041c
    274 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D28			0x0420
    275 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D29			0x0424
    276 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D30			0x0428
    277 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D31			0x042c
    278 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A16			0x0430
    279 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A17			0x0434
    280 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A18			0x0438
    281 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A19			0x043c
    282 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A20			0x0440
    283 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A21			0x0444
    284 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A22			0x0448
    285 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A23			0x044c
    286 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A24			0x0450
    287 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A25			0x0454
    288 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A26			0x0458
    289 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A27			0x045c
    290 #define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0			0x0460
    291 #define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1			0x0464
    292 #define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2			0x0468
    293 #define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3			0x046c
    294 #define IOMUXC_SW_PAD_CTL_PAD_EIM_OE			0x0470
    295 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0			0x0474
    296 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1			0x0478
    297 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS2			0x047c
    298 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS3			0x0480
    299 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS4			0x0484
    300 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS5			0x0488
    301 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DTACK			0x048c
    302 #define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT			0x0490
    303 #define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA			0x0494
    304 #define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK			0x0498
    305 #define IOMUXC_SW_PAD_CTL_PAD_EIM_RW			0x049c
    306 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CRE			0x04a0
    307 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS			0x04a4
    308 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS			0x04a8
    309 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE			0x04ac
    310 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0		0x04b0
    311 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1		0x04b4
    312 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK		0x04b8
    313 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0		0x04bc
    314 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1		0x04c0
    315 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2		0x04c4
    316 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3		0x04c8
    317 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0			0x04cc
    318 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1			0x04d0
    319 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0			0x04d4
    320 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1			0x04d8
    321 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2			0x04dc
    322 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3			0x04e0
    323 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B		0x04e4
    324 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B		0x04e8
    325 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE			0x04ec
    326 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE			0x04f0
    327 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B		0x04f4
    328 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0			0x04f8
    329 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1			0x04fc
    330 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2			0x0500
    331 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3			0x0504
    332 #define IOMUXC_SW_PAD_CTL_PAD_EIM_SDBA2			0x0508
    333 #define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT1		0x050c
    334 #define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT0		0x0510
    335 #define IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND			0x0514
    336 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0			0x0518
    337 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1			0x051c
    338 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2			0x0520
    339 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3			0x0524
    340 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4			0x0528
    341 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5			0x052c
    342 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6			0x0530
    343 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7			0x0534
    344 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT		0x0538
    345 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D15			0x053c
    346 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D14			0x0540
    347 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D13			0x0544
    348 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D12			0x0548
    349 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D11			0x054c
    350 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D10			0x0550
    351 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D9			0x0554
    352 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D8			0x0558
    353 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7			0x055c
    354 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6			0x0560
    355 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5			0x0564
    356 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4			0x0568
    357 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3			0x056c
    358 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2			0x0570
    359 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1			0x0574
    360 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0			0x0578
    361 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D8			0x057c
    362 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D9			0x0580
    363 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D10			0x0584
    364 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D11			0x0588
    365 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D12			0x058c
    366 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D13			0x0590
    367 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D14			0x0594
    368 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D15			0x0598
    369 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D16			0x059c
    370 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D17			0x05a0
    371 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D18			0x05a4
    372 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D19			0x05a8
    373 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_VSYNC		0x05ac
    374 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_HSYNC		0x05b0
    375 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_PIXCLK		0x05b4
    376 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_MCLK			0x05b8
    377 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D12			0x05bc
    378 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D13			0x05c0
    379 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D14			0x05c4
    380 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D15			0x05c8
    381 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D16			0x05cc
    382 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D17			0x05d0
    383 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D18			0x05d4
    384 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D19			0x05d8
    385 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_VSYNC		0x05dc
    386 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_HSYNC		0x05e0
    387 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_PIXCLK		0x05e4
    388 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_CLK			0x05e8
    389 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_DAT			0x05ec
    390 #define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_TXD		0x05f0
    391 #define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_RXD		0x05f4
    392 #define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK		0x05f8
    393 #define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_FS		0x05fc
    394 #define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI		0x0600
    395 #define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO		0x0604
    396 #define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0			0x0608
    397 #define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1			0x060c
    398 #define IOMUXC_SW_PAD_CTL_PAD_CSPI1_RDY			0x0610
    399 #define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK		0x0614
    400 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RXD			0x0618
    401 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TXD			0x061c
    402 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS			0x0620
    403 #define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS			0x0624
    404 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RXD			0x0628
    405 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TXD			0x062c
    406 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RXD			0x0630
    407 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TXD			0x0634
    408 #define IOMUXC_SW_PAD_CTL_PAD_OWIRE_LINE		0x0638
    409 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0			0x063c
    410 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1			0x0640
    411 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2			0x0644
    412 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3			0x0648
    413 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0			0x064c
    414 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1			0x0650
    415 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2			0x0654
    416 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3			0x0658
    417 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4			0x065c
    418 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL5			0x0660
    419 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK			0x0664
    420 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS			0x0668
    421 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI			0x066c
    422 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB		0x0670
    423 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD			0x0674
    424 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_CLK			0x0678
    425 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DIR			0x067c
    426 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_STP			0x0680
    427 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_NXT			0x0684
    428 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA0		0x0688
    429 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA1		0x068c
    430 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA2		0x0690
    431 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA3		0x0694
    432 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA4		0x0698
    433 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA5		0x069c
    434 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA6		0x06a0
    435 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA7		0x06a4
    436 #define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11			0x06a8
    437 #define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12			0x06ac
    438 #define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13			0x06b0
    439 #define IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS			0x06b4
    440 #define IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS			0x06b8
    441 #define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIN		0x06bc
    442 #define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIO		0x06c0
    443 #define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_CLK		0x06c4
    444 #define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_RS		0x06c8
    445 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0		0x06cc
    446 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1		0x06d0
    447 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2		0x06d4
    448 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3		0x06d8
    449 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4		0x06dc
    450 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5		0x06e0
    451 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6		0x06e4
    452 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7		0x06e8
    453 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8		0x06ec
    454 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9		0x06f0
    455 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10		0x06f4
    456 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11		0x06f8
    457 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12		0x06fc
    458 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13		0x0700
    459 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14		0x0704
    460 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15		0x0708
    461 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16		0x070c
    462 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17		0x0710
    463 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT18		0x0714
    464 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT19		0x0718
    465 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT20		0x071c
    466 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT21		0x0720
    467 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT22		0x0724
    468 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT23		0x0728
    469 #define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN3			0x072c
    470 #define IOMUXC_SW_PAD_CTL_PAD_DI1_DISP_CLK		0x0730
    471 #define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN2			0x0734
    472 #define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN15			0x0738
    473 #define IOMUXC_SW_PAD_CTL_PAD_DI_GP1			0x073c
    474 #define IOMUXC_SW_PAD_CTL_PAD_DI_GP2			0x0740
    475 #define IOMUXC_SW_PAD_CTL_PAD_DI_GP3			0x0744
    476 #define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN4			0x0748
    477 #define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN2			0x074c
    478 #define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN3			0x0750
    479 #define IOMUXC_SW_PAD_CTL_PAD_DI2_DISP_CLK		0x0754
    480 #define IOMUXC_SW_PAD_CTL_PAD_DI_GP4			0x0758
    481 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT0		0x075c
    482 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT1		0x0760
    483 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT2		0x0764
    484 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT3		0x0768
    485 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT4		0x076c
    486 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT5		0x0770
    487 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT6		0x0774
    488 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT7		0x0778
    489 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT8		0x077c
    490 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT9		0x0780
    491 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT10		0x0784
    492 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT11		0x0788
    493 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT12		0x078c
    494 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT13		0x0790
    495 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT14		0x0794
    496 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT15		0x0798
    497 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD			0x079c
    498 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK			0x07a0
    499 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0			0x07a4
    500 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1			0x07a8
    501 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2			0x07ac
    502 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3			0x07b0
    503 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_0			0x07b4
    504 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_1			0x07b8
    505 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD			0x07bc
    506 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK			0x07c0
    507 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0			0x07c4
    508 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1			0x07c8
    509 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2			0x07cc
    510 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3			0x07d0
    511 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_2			0x07d4
    512 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_3			0x07d8
    513 #define IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B		0x07dc
    514 #define IOMUXC_SW_PAD_CTL_PAD_POR_B			0x07e0
    515 #define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1		0x07e4
    516 #define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0		0x07e8
    517 #define IOMUXC_SW_PAD_CTL_PAD_PMIC_RDY			0x07ec
    518 #define IOMUXC_SW_PAD_CTL_PAD_CKIL			0x07f0
    519 #define IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ		0x07f4
    520 #define IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ		0x07f8
    521 #define IOMUXC_SW_PAD_CTL_PAD_PMIC_INT_REQ		0x07fc
    522 #define IOMUXC_SW_PAD_CTL_PAD_CLK_SS			0x0800
    523 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_4			0x0804
    524 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_5			0x0808
    525 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_6			0x080c
    526 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_7			0x0810
    527 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_8			0x0814
    528 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_9			0x0818
    529 #define IOMUXC_SW_PAD_CTL_GRP_CSI2_PKE0			0x081c
    530 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKS			0x0820
    531 #define IOMUXC_SW_PAD_CTL_GRP_EIM_SR1			0x0824
    532 #define IOMUXC_SW_PAD_CTL_GRP_DISP2_PKE0		0x0828
    533 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_B4			0x082c
    534 #define IOMUXC_SW_PAD_CTL_GRP_INDDR			0x0830
    535 #define IOMUXC_SW_PAD_CTL_GRP_EIM_SR2			0x0834
    536 #define IOMUXC_SW_PAD_CTL_GRP_PKEDDR			0x0838
    537 #define IOMUXC_SW_PAD_CTL_GRP_DDR_A0			0x083c
    538 #define IOMUXC_SW_PAD_CTL_GRP_EMI_PKE0			0x0840
    539 #define IOMUXC_SW_PAD_CTL_GRP_EIM_SR3			0x0844
    540 #define IOMUXC_SW_PAD_CTL_GRP_DDR_A1			0x0848
    541 #define IOMUXC_SW_PAD_CTL_GRP_DDRAPUS			0x084c
    542 #define IOMUXC_SW_PAD_CTL_GRP_EIM_SR4			0x0850
    543 #define IOMUXC_SW_PAD_CTL_GRP_EMI_SR5			0x0854
    544 #define IOMUXC_SW_PAD_CTL_GRP_EMI_SR6			0x0858
    545 #define IOMUXC_SW_PAD_CTL_GRP_HYSDDR0			0x085c
    546 #define IOMUXC_SW_PAD_CTL_GRP_CSI1_PKE0			0x0860
    547 #define IOMUXC_SW_PAD_CTL_GRP_HYSDDR1			0x0864
    548 #define IOMUXC_SW_PAD_CTL_GRP_DISP1_PKE0		0x0868
    549 #define IOMUXC_SW_PAD_CTL_GRP_HYSDDR2			0x086c
    550 #define IOMUXC_SW_PAD_CTL_GRP_HVDDR			0x0870
    551 #define IOMUXC_SW_PAD_CTL_GRP_HYSDDR3			0x0874
    552 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B0		0x0878
    553 #define IOMUXC_SW_PAD_CTL_GRP_DDRAPKS			0x087c
    554 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B1		0x0880
    555 #define IOMUXC_SW_PAD_CTL_GRP_DDRPUS			0x0884
    556 #define IOMUXC_SW_PAD_CTL_GRP_EIM_DS1			0x0888
    557 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B2		0x088c
    558 #define IOMUXC_SW_PAD_CTL_GRP_PKEADDR			0x0890
    559 #define IOMUXC_SW_PAD_CTL_GRP_EIM_DS2			0x0894
    560 #define IOMUXC_SW_PAD_CTL_GRP_EIM_DS3			0x0898
    561 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B4		0x089c
    562 #define IOMUXC_SW_PAD_CTL_GRP_INMODE1			0x08a0
    563 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_B0			0x08a4
    564 #define IOMUXC_SW_PAD_CTL_GRP_EIM_DS4			0x08a8
    565 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_B1			0x08ac
    566 #define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A0			0x08b0
    567 #define IOMUXC_SW_PAD_CTL_GRP_EMI_DS5			0x08b4
    568 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_B2			0x08b8
    569 #define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A1			0x08bc
    570 #define IOMUXC_SW_PAD_CTL_GRP_EMI_DS6			0x08c0
    571 #define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT	0x08c4
    572 #define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT	0x08c8
    573 #define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT	0x08cc
    574 #define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT	0x08d0
    575 #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT	0x08d4
    576 #define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT	0x08d8
    577 #define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT	0x08dc
    578 #define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT	0x08e0
    579 #define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT	0x08e4
    580 #define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT	0x08e8
    581 #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT	0x08ec
    582 #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT	0x08f0
    583 #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT	0x08f4
    584 #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT	0x08f8
    585 #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT	0x08fc
    586 #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT	0x0900
    587 #define IOMUXC_CCM_IPP_DI0_CLK_SELECT_INPUT		0x0904
    588 #define IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT		0x0908
    589 #define IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT		0x090c
    590 #define IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT		0x0910
    591 #define IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT	0x0914
    592 #define IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT		0x0918
    593 #define IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT		0x091c
    594 #define IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT		0x0920
    595 #define IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT		0x0924
    596 #define IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT		0x0928
    597 #define IOMUXC_DPLLIP1_L1T_TOG_EN_SELECT_INPUT		0x092c
    598 #define IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT	0x0930
    599 #define IOMUXC_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT	0x0934
    600 #define IOMUXC_EMI_IPP_IND_RDY_INT_SELECT_INPUT		0x0938
    601 #define IOMUXC_ESDHC3_IPP_DAT0_IN_SELECT_INPUT		0x093c
    602 #define IOMUXC_ESDHC3_IPP_DAT1_IN_SELECT_INPUT		0x0940
    603 #define IOMUXC_ESDHC3_IPP_DAT2_IN_SELECT_INPUT		0x0944
    604 #define IOMUXC_ESDHC3_IPP_DAT3_IN_SELECT_INPUT		0x0948
    605 #define IOMUXC_FEC_FEC_COL_SELECT_INPUT			0x094c
    606 #define IOMUXC_FEC_FEC_CRS_SELECT_INPUT			0x0950
    607 #define IOMUXC_FEC_FEC_MDI_SELECT_INPUT			0x0954
    608 #define IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT		0x0958
    609 #define IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT		0x095c
    610 #define IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT		0x0960
    611 #define IOMUXC_FEC_FEC_RDATA_3_SELECT_INPUT		0x0964
    612 #define IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT		0x0968
    613 #define IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT		0x096c
    614 #define IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT		0x0970
    615 #define IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT		0x0974
    616 #define IOMUXC_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT	0x0978
    617 #define IOMUXC_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT	0x097c
    618 #define IOMUXC_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT	0x0980
    619 #define IOMUXC_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT	0x0984
    620 #define IOMUXC_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT	0x0988
    621 #define IOMUXC_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT	0x098c
    622 #define IOMUXC_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT	0x0990
    623 #define IOMUXC_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT	0x0994
    624 #define IOMUXC_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT	0x0998
    625 #define IOMUXC_HSC_MIPI_MIX_PAR0_VSYNC_SELECT_INPUT	0x09a4
    626 #define IOMUXC_HSC_MIPI_MIX_PAR1_DI_WAIT_SELECT_INPUT	0x09a8
    627 #define IOMUXC_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT	0x09ac
    628 #define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT		0x09b0
    629 #define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT		0x09b4
    630 #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT		0x09b8
    631 #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT		0x09bc
    632 #define IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT	0x09c0
    633 #define IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT	0x09c4
    634 #define IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT		0x09c8
    635 #define IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT		0x09cc
    636 #define IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT		0x09d0
    637 #define IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT		0x09d4
    638 #define IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT		0x09d8
    639 #define IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT		0x09dc
    640 #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT	0x09e0
    641 #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT	0x09e4
    642 #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT	0x09e8
    643 #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT	0x09ec
    644 #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT	0x09f0
    645 #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT	0x09f4
    646 #define IOMUXC_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT	0x09f8
    647 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT	0x09fc
    648 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT	0x0a00
    649 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT	0x0a04
    650 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT	0x0a08
    651 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT	0x0a0c
    652 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT	0x0a10
    653 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT	0x0a14
    654 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT	0x0a18
    655 #define IOMUXC_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT	0x0a1c
    656 #define IOMUXC_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT	0x0a20
    657 #define IOMUXC_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT	0x0a24
    658 
    659 /* MUX & PAD Control */
    660 
    661 #define MUX_PIN(name)				\
    662 	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name,	\
    663 	    IOMUXC_SW_PAD_CTL_PAD_##name)
    664 
    665 #endif /* _IMX51_IOMUXREG_H */
    666 
    667