1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2022 Emil Renner Berthing <kernel (at) esmil.dk> 4 * Copyright 2022 StarFive Technology Co., Ltd. 5 */ 6 7 #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ 8 #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ 9 10 /* PLL clocks */ 11 #define JH7110_PLLCLK_PLL0_OUT 0 12 #define JH7110_PLLCLK_PLL1_OUT 1 13 #define JH7110_PLLCLK_PLL2_OUT 2 14 #define JH7110_PLLCLK_END 3 15 16 /* SYSCRG clocks */ 17 #define JH7110_SYSCLK_CPU_ROOT 0 18 #define JH7110_SYSCLK_CPU_CORE 1 19 #define JH7110_SYSCLK_CPU_BUS 2 20 #define JH7110_SYSCLK_GPU_ROOT 3 21 #define JH7110_SYSCLK_PERH_ROOT 4 22 #define JH7110_SYSCLK_BUS_ROOT 5 23 #define JH7110_SYSCLK_NOCSTG_BUS 6 24 #define JH7110_SYSCLK_AXI_CFG0 7 25 #define JH7110_SYSCLK_STG_AXIAHB 8 26 #define JH7110_SYSCLK_AHB0 9 27 #define JH7110_SYSCLK_AHB1 10 28 #define JH7110_SYSCLK_APB_BUS 11 29 #define JH7110_SYSCLK_APB0 12 30 #define JH7110_SYSCLK_PLL0_DIV2 13 31 #define JH7110_SYSCLK_PLL1_DIV2 14 32 #define JH7110_SYSCLK_PLL2_DIV2 15 33 #define JH7110_SYSCLK_AUDIO_ROOT 16 34 #define JH7110_SYSCLK_MCLK_INNER 17 35 #define JH7110_SYSCLK_MCLK 18 36 #define JH7110_SYSCLK_MCLK_OUT 19 37 #define JH7110_SYSCLK_ISP_2X 20 38 #define JH7110_SYSCLK_ISP_AXI 21 39 #define JH7110_SYSCLK_GCLK0 22 40 #define JH7110_SYSCLK_GCLK1 23 41 #define JH7110_SYSCLK_GCLK2 24 42 #define JH7110_SYSCLK_CORE 25 43 #define JH7110_SYSCLK_CORE1 26 44 #define JH7110_SYSCLK_CORE2 27 45 #define JH7110_SYSCLK_CORE3 28 46 #define JH7110_SYSCLK_CORE4 29 47 #define JH7110_SYSCLK_DEBUG 30 48 #define JH7110_SYSCLK_RTC_TOGGLE 31 49 #define JH7110_SYSCLK_TRACE0 32 50 #define JH7110_SYSCLK_TRACE1 33 51 #define JH7110_SYSCLK_TRACE2 34 52 #define JH7110_SYSCLK_TRACE3 35 53 #define JH7110_SYSCLK_TRACE4 36 54 #define JH7110_SYSCLK_TRACE_COM 37 55 #define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 56 #define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 57 #define JH7110_SYSCLK_OSC_DIV2 40 58 #define JH7110_SYSCLK_PLL1_DIV4 41 59 #define JH7110_SYSCLK_PLL1_DIV8 42 60 #define JH7110_SYSCLK_DDR_BUS 43 61 #define JH7110_SYSCLK_DDR_AXI 44 62 #define JH7110_SYSCLK_GPU_CORE 45 63 #define JH7110_SYSCLK_GPU_CORE_CLK 46 64 #define JH7110_SYSCLK_GPU_SYS_CLK 47 65 #define JH7110_SYSCLK_GPU_APB 48 66 #define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 67 #define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 68 #define JH7110_SYSCLK_ISP_TOP_CORE 51 69 #define JH7110_SYSCLK_ISP_TOP_AXI 52 70 #define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 71 #define JH7110_SYSCLK_HIFI4_CORE 54 72 #define JH7110_SYSCLK_HIFI4_AXI 55 73 #define JH7110_SYSCLK_AXI_CFG1_MAIN 56 74 #define JH7110_SYSCLK_AXI_CFG1_AHB 57 75 #define JH7110_SYSCLK_VOUT_SRC 58 76 #define JH7110_SYSCLK_VOUT_AXI 59 77 #define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 78 #define JH7110_SYSCLK_VOUT_TOP_AHB 61 79 #define JH7110_SYSCLK_VOUT_TOP_AXI 62 80 #define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63 81 #define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64 82 #define JH7110_SYSCLK_JPEGC_AXI 65 83 #define JH7110_SYSCLK_CODAJ12_AXI 66 84 #define JH7110_SYSCLK_CODAJ12_CORE 67 85 #define JH7110_SYSCLK_CODAJ12_APB 68 86 #define JH7110_SYSCLK_VDEC_AXI 69 87 #define JH7110_SYSCLK_WAVE511_AXI 70 88 #define JH7110_SYSCLK_WAVE511_BPU 71 89 #define JH7110_SYSCLK_WAVE511_VCE 72 90 #define JH7110_SYSCLK_WAVE511_APB 73 91 #define JH7110_SYSCLK_VDEC_JPG 74 92 #define JH7110_SYSCLK_VDEC_MAIN 75 93 #define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 94 #define JH7110_SYSCLK_VENC_AXI 77 95 #define JH7110_SYSCLK_WAVE420L_AXI 78 96 #define JH7110_SYSCLK_WAVE420L_BPU 79 97 #define JH7110_SYSCLK_WAVE420L_VCE 80 98 #define JH7110_SYSCLK_WAVE420L_APB 81 99 #define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 100 #define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83 101 #define JH7110_SYSCLK_AXI_CFG0_MAIN 84 102 #define JH7110_SYSCLK_AXI_CFG0_HIFI4 85 103 #define JH7110_SYSCLK_AXIMEM2_AXI 86 104 #define JH7110_SYSCLK_QSPI_AHB 87 105 #define JH7110_SYSCLK_QSPI_APB 88 106 #define JH7110_SYSCLK_QSPI_REF_SRC 89 107 #define JH7110_SYSCLK_QSPI_REF 90 108 #define JH7110_SYSCLK_SDIO0_AHB 91 109 #define JH7110_SYSCLK_SDIO1_AHB 92 110 #define JH7110_SYSCLK_SDIO0_SDCARD 93 111 #define JH7110_SYSCLK_SDIO1_SDCARD 94 112 #define JH7110_SYSCLK_USB_125M 95 113 #define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 114 #define JH7110_SYSCLK_GMAC1_AHB 97 115 #define JH7110_SYSCLK_GMAC1_AXI 98 116 #define JH7110_SYSCLK_GMAC_SRC 99 117 #define JH7110_SYSCLK_GMAC1_GTXCLK 100 118 #define JH7110_SYSCLK_GMAC1_RMII_RTX 101 119 #define JH7110_SYSCLK_GMAC1_PTP 102 120 #define JH7110_SYSCLK_GMAC1_RX 103 121 #define JH7110_SYSCLK_GMAC1_RX_INV 104 122 #define JH7110_SYSCLK_GMAC1_TX 105 123 #define JH7110_SYSCLK_GMAC1_TX_INV 106 124 #define JH7110_SYSCLK_GMAC1_GTXC 107 125 #define JH7110_SYSCLK_GMAC0_GTXCLK 108 126 #define JH7110_SYSCLK_GMAC0_PTP 109 127 #define JH7110_SYSCLK_GMAC_PHY 110 128 #define JH7110_SYSCLK_GMAC0_GTXC 111 129 #define JH7110_SYSCLK_IOMUX_APB 112 130 #define JH7110_SYSCLK_MAILBOX_APB 113 131 #define JH7110_SYSCLK_INT_CTRL_APB 114 132 #define JH7110_SYSCLK_CAN0_APB 115 133 #define JH7110_SYSCLK_CAN0_TIMER 116 134 #define JH7110_SYSCLK_CAN0_CAN 117 135 #define JH7110_SYSCLK_CAN1_APB 118 136 #define JH7110_SYSCLK_CAN1_TIMER 119 137 #define JH7110_SYSCLK_CAN1_CAN 120 138 #define JH7110_SYSCLK_PWM_APB 121 139 #define JH7110_SYSCLK_WDT_APB 122 140 #define JH7110_SYSCLK_WDT_CORE 123 141 #define JH7110_SYSCLK_TIMER_APB 124 142 #define JH7110_SYSCLK_TIMER0 125 143 #define JH7110_SYSCLK_TIMER1 126 144 #define JH7110_SYSCLK_TIMER2 127 145 #define JH7110_SYSCLK_TIMER3 128 146 #define JH7110_SYSCLK_TEMP_APB 129 147 #define JH7110_SYSCLK_TEMP_CORE 130 148 #define JH7110_SYSCLK_SPI0_APB 131 149 #define JH7110_SYSCLK_SPI1_APB 132 150 #define JH7110_SYSCLK_SPI2_APB 133 151 #define JH7110_SYSCLK_SPI3_APB 134 152 #define JH7110_SYSCLK_SPI4_APB 135 153 #define JH7110_SYSCLK_SPI5_APB 136 154 #define JH7110_SYSCLK_SPI6_APB 137 155 #define JH7110_SYSCLK_I2C0_APB 138 156 #define JH7110_SYSCLK_I2C1_APB 139 157 #define JH7110_SYSCLK_I2C2_APB 140 158 #define JH7110_SYSCLK_I2C3_APB 141 159 #define JH7110_SYSCLK_I2C4_APB 142 160 #define JH7110_SYSCLK_I2C5_APB 143 161 #define JH7110_SYSCLK_I2C6_APB 144 162 #define JH7110_SYSCLK_UART0_APB 145 163 #define JH7110_SYSCLK_UART0_CORE 146 164 #define JH7110_SYSCLK_UART1_APB 147 165 #define JH7110_SYSCLK_UART1_CORE 148 166 #define JH7110_SYSCLK_UART2_APB 149 167 #define JH7110_SYSCLK_UART2_CORE 150 168 #define JH7110_SYSCLK_UART3_APB 151 169 #define JH7110_SYSCLK_UART3_CORE 152 170 #define JH7110_SYSCLK_UART4_APB 153 171 #define JH7110_SYSCLK_UART4_CORE 154 172 #define JH7110_SYSCLK_UART5_APB 155 173 #define JH7110_SYSCLK_UART5_CORE 156 174 #define JH7110_SYSCLK_PWMDAC_APB 157 175 #define JH7110_SYSCLK_PWMDAC_CORE 158 176 #define JH7110_SYSCLK_SPDIF_APB 159 177 #define JH7110_SYSCLK_SPDIF_CORE 160 178 #define JH7110_SYSCLK_I2STX0_APB 161 179 #define JH7110_SYSCLK_I2STX0_BCLK_MST 162 180 #define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 181 #define JH7110_SYSCLK_I2STX0_LRCK_MST 164 182 #define JH7110_SYSCLK_I2STX0_BCLK 165 183 #define JH7110_SYSCLK_I2STX0_BCLK_INV 166 184 #define JH7110_SYSCLK_I2STX0_LRCK 167 185 #define JH7110_SYSCLK_I2STX1_APB 168 186 #define JH7110_SYSCLK_I2STX1_BCLK_MST 169 187 #define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 188 #define JH7110_SYSCLK_I2STX1_LRCK_MST 171 189 #define JH7110_SYSCLK_I2STX1_BCLK 172 190 #define JH7110_SYSCLK_I2STX1_BCLK_INV 173 191 #define JH7110_SYSCLK_I2STX1_LRCK 174 192 #define JH7110_SYSCLK_I2SRX_APB 175 193 #define JH7110_SYSCLK_I2SRX_BCLK_MST 176 194 #define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 195 #define JH7110_SYSCLK_I2SRX_LRCK_MST 178 196 #define JH7110_SYSCLK_I2SRX_BCLK 179 197 #define JH7110_SYSCLK_I2SRX_BCLK_INV 180 198 #define JH7110_SYSCLK_I2SRX_LRCK 181 199 #define JH7110_SYSCLK_PDM_DMIC 182 200 #define JH7110_SYSCLK_PDM_APB 183 201 #define JH7110_SYSCLK_TDM_AHB 184 202 #define JH7110_SYSCLK_TDM_APB 185 203 #define JH7110_SYSCLK_TDM_INTERNAL 186 204 #define JH7110_SYSCLK_TDM_TDM 187 205 #define JH7110_SYSCLK_TDM_TDM_INV 188 206 #define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 207 208 #define JH7110_SYSCLK_END 190 209 210 /* AONCRG clocks */ 211 #define JH7110_AONCLK_OSC_DIV4 0 212 #define JH7110_AONCLK_APB_FUNC 1 213 #define JH7110_AONCLK_GMAC0_AHB 2 214 #define JH7110_AONCLK_GMAC0_AXI 3 215 #define JH7110_AONCLK_GMAC0_RMII_RTX 4 216 #define JH7110_AONCLK_GMAC0_TX 5 217 #define JH7110_AONCLK_GMAC0_TX_INV 6 218 #define JH7110_AONCLK_GMAC0_RX 7 219 #define JH7110_AONCLK_GMAC0_RX_INV 8 220 #define JH7110_AONCLK_OTPC_APB 9 221 #define JH7110_AONCLK_RTC_APB 10 222 #define JH7110_AONCLK_RTC_INTERNAL 11 223 #define JH7110_AONCLK_RTC_32K 12 224 #define JH7110_AONCLK_RTC_CAL 13 225 226 #define JH7110_AONCLK_END 14 227 228 /* STGCRG clocks */ 229 #define JH7110_STGCLK_HIFI4_CLK_CORE 0 230 #define JH7110_STGCLK_USB0_APB 1 231 #define JH7110_STGCLK_USB0_UTMI_APB 2 232 #define JH7110_STGCLK_USB0_AXI 3 233 #define JH7110_STGCLK_USB0_LPM 4 234 #define JH7110_STGCLK_USB0_STB 5 235 #define JH7110_STGCLK_USB0_APP_125 6 236 #define JH7110_STGCLK_USB0_REFCLK 7 237 #define JH7110_STGCLK_PCIE0_AXI_MST0 8 238 #define JH7110_STGCLK_PCIE0_APB 9 239 #define JH7110_STGCLK_PCIE0_TL 10 240 #define JH7110_STGCLK_PCIE1_AXI_MST0 11 241 #define JH7110_STGCLK_PCIE1_APB 12 242 #define JH7110_STGCLK_PCIE1_TL 13 243 #define JH7110_STGCLK_PCIE_SLV_MAIN 14 244 #define JH7110_STGCLK_SEC_AHB 15 245 #define JH7110_STGCLK_SEC_MISC_AHB 16 246 #define JH7110_STGCLK_GRP0_MAIN 17 247 #define JH7110_STGCLK_GRP0_BUS 18 248 #define JH7110_STGCLK_GRP0_STG 19 249 #define JH7110_STGCLK_GRP1_MAIN 20 250 #define JH7110_STGCLK_GRP1_BUS 21 251 #define JH7110_STGCLK_GRP1_STG 22 252 #define JH7110_STGCLK_GRP1_HIFI 23 253 #define JH7110_STGCLK_E2_RTC 24 254 #define JH7110_STGCLK_E2_CORE 25 255 #define JH7110_STGCLK_E2_DBG 26 256 #define JH7110_STGCLK_DMA1P_AXI 27 257 #define JH7110_STGCLK_DMA1P_AHB 28 258 259 #define JH7110_STGCLK_END 29 260 261 /* ISPCRG clocks */ 262 #define JH7110_ISPCLK_DOM4_APB_FUNC 0 263 #define JH7110_ISPCLK_MIPI_RX0_PXL 1 264 #define JH7110_ISPCLK_DVP_INV 2 265 #define JH7110_ISPCLK_M31DPHY_CFG_IN 3 266 #define JH7110_ISPCLK_M31DPHY_REF_IN 4 267 #define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5 268 #define JH7110_ISPCLK_VIN_APB 6 269 #define JH7110_ISPCLK_VIN_SYS 7 270 #define JH7110_ISPCLK_VIN_PIXEL_IF0 8 271 #define JH7110_ISPCLK_VIN_PIXEL_IF1 9 272 #define JH7110_ISPCLK_VIN_PIXEL_IF2 10 273 #define JH7110_ISPCLK_VIN_PIXEL_IF3 11 274 #define JH7110_ISPCLK_VIN_P_AXI_WR 12 275 #define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13 276 277 #define JH7110_ISPCLK_END 14 278 279 /* VOUTCRG clocks */ 280 #define JH7110_VOUTCLK_APB 0 281 #define JH7110_VOUTCLK_DC8200_PIX 1 282 #define JH7110_VOUTCLK_DSI_SYS 2 283 #define JH7110_VOUTCLK_TX_ESC 3 284 #define JH7110_VOUTCLK_DC8200_AXI 4 285 #define JH7110_VOUTCLK_DC8200_CORE 5 286 #define JH7110_VOUTCLK_DC8200_AHB 6 287 #define JH7110_VOUTCLK_DC8200_PIX0 7 288 #define JH7110_VOUTCLK_DC8200_PIX1 8 289 #define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9 290 #define JH7110_VOUTCLK_DSITX_APB 10 291 #define JH7110_VOUTCLK_DSITX_SYS 11 292 #define JH7110_VOUTCLK_DSITX_DPI 12 293 #define JH7110_VOUTCLK_DSITX_TXESC 13 294 #define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14 295 #define JH7110_VOUTCLK_HDMI_TX_MCLK 15 296 #define JH7110_VOUTCLK_HDMI_TX_BCLK 16 297 #define JH7110_VOUTCLK_HDMI_TX_SYS 17 298 299 #define JH7110_VOUTCLK_END 18 300 301 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ 302
Indexes created Wed Oct 01 19:09:53 GMT 2025