1 /* $NetBSD: pte.h,v 1.23 2020/05/04 18:36:24 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_PTE_H_ 39 #define _ARM_PTE_H_ 40 41 /* 42 * The ARM MMU architecture was introduced with ARM v3 (previous ARM 43 * architecture versions used an optional off-CPU memory controller 44 * to perform address translation). 45 * 46 * The ARM MMU consists of a TLB and translation table walking logic. 47 * There is typically one TLB per memory interface (or, put another 48 * way, one TLB per software-visible cache). 49 * 50 * The ARM MMU is capable of mapping memory in the following chunks: 51 * 52 * 16M SuperSections (L1 table, ARMv6+) 53 * 54 * 1M Sections (L1 table) 55 * 56 * 64K Large Pages (L2 table) 57 * 58 * 4K Small Pages (L2 table) 59 * 60 * 1K Tiny Pages (L2 table) 61 * 62 * There are two types of L2 tables: Coarse Tables and Fine Tables (not 63 * available on ARMv6+). Coarse Tables can map Large and Small Pages. 64 * Fine Tables can map Tiny Pages. 65 * 66 * Coarse Tables can define 4 Subpages within Large and Small pages. 67 * Subpages define different permissions for each Subpage within 68 * a Page. ARMv6 format Coarse Tables have no subpages. 69 * 70 * Coarse Tables are 1K in length. Fine tables are 4K in length. 71 * 72 * The Translation Table Base register holds the pointer to the 73 * L1 Table. The L1 Table is a 16K contiguous chunk of memory 74 * aligned to a 16K boundary. Each entry in the L1 Table maps 75 * 1M of virtual address space, either via a Section mapping or 76 * via an L2 Table. 77 * 78 * ARMv6+ has a second TTBR register which can be used if any of the 79 * upper address bits are non-zero (think kernel). For NetBSD, this 80 * would be 1 upper bit splitting user/kernel in a 2GB/2GB split. 81 * This would also reduce the size of the L1 Table to 8K. 82 * 83 * In addition, the Fast Context Switching Extension (FCSE) is available 84 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating 85 * TLB/cache flushes on context switch by use of a smaller address space 86 * and a "process ID" that modifies the virtual address before being 87 * presented to the translation logic. 88 */ 89 90 #ifndef _LOCORE 91 typedef uint32_t pd_entry_t; /* L1 table entry */ 92 #ifndef __BSD_PTENTRY_T__ 93 #define __BSD_PTENTRY_T__ 94 typedef uint32_t pt_entry_t; 95 #define PRIxPTE PRIx32 96 #endif 97 #endif /* _LOCORE */ 98 99 #define L1_SS_SIZE 0x01000000 /* 16M */ 100 #define L1_SS_OFFSET (L1_SS_SIZE - 1) 101 #define L1_SS_FRAME (~L1_SS_OFFSET) 102 #define L1_SS_SHIFT 24 103 104 #define L1_S_SIZE 0x00100000 /* 1M */ 105 #define L1_S_OFFSET (L1_S_SIZE - 1) 106 #define L1_S_FRAME (~L1_S_OFFSET) 107 #define L1_S_SHIFT 20 108 109 #define L2_L_SIZE 0x00010000 /* 64K */ 110 #define L2_L_OFFSET (L2_L_SIZE - 1) 111 #define L2_L_FRAME (~L2_L_OFFSET) 112 #define L2_L_SHIFT 16 113 114 #define L2_S_SEGSIZE (PAGE_SIZE * L2_S_SIZE / 4) 115 #define L2_S_SIZE 0x00001000 /* 4K */ 116 #define L2_S_OFFSET (L2_S_SIZE - 1) 117 #define L2_S_FRAME (~L2_S_OFFSET) 118 #define L2_S_SHIFT 12 119 120 #define L2_T_SIZE 0x00000400 /* 1K */ 121 #define L2_T_OFFSET (L2_T_SIZE - 1) 122 #define L2_T_FRAME (~L2_T_OFFSET) 123 #define L2_T_SHIFT 10 124 125 /* 126 * The NetBSD VM implementation only works on whole pages (4K), 127 * whereas the ARM MMU's Coarse tables are sized in terms of 1K 128 * (16K L1 table, 1K L2 table). 129 * 130 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2 131 * table. 132 */ 133 #define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */ 134 #define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */ 135 136 #define L1_TABLE_SIZE 0x4000 /* 16K */ 137 #define L2_TABLE_SIZE 0x1000 /* 4K */ 138 139 /* 140 * The new pmap deals with the 1KB coarse L2 tables by 141 * allocating them from a pool. Until every port has been converted, 142 * keep the old L2_TABLE_SIZE define lying around. Converted ports 143 * should use L2_TABLE_SIZE_REAL until then. 144 */ 145 #define L2_TABLE_SIZE_REAL 0x400 /* 1K */ 146 147 #define L1TT_SIZE 0x2000 /* 8K */ 148 149 /* 150 * ARM L1 Descriptors 151 */ 152 153 #define L1_TYPE_INV 0x00 /* Invalid (fault) */ 154 #define L1_TYPE_C 0x01 /* Coarse L2 */ 155 #define L1_TYPE_S 0x02 /* Section */ 156 #define L1_TYPE_F 0x03 /* Fine L2 */ 157 #define L1_TYPE_MASK 0x03 /* mask of type bits */ 158 159 /* L1 Section Descriptor */ 160 #define L1_S_B 0x00000004 /* bufferable Section */ 161 #define L1_S_C 0x00000008 /* cacheable Section */ 162 #define L1_S_IMP 0x00000010 /* implementation defined */ 163 #define L1_S_DOM(x) ((x) << 5) /* domain */ 164 #define L1_S_DOM_MASK L1_S_DOM(0xf) 165 #define L1_S_AP(x) ((x) << 10) /* access permissions */ 166 #define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ 167 168 #define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ 169 #define L1_S_XS_TEX(x) ((x) << 12) /* Type Extension */ 170 #define L1_S_V6_TEX(x) L1_S_XS_TEX(x) 171 #define L1_S_V6_P 0x00000200 /* ECC enable for this section */ 172 #define L1_S_V6_SUPER 0x00040000 /* ARMv6 SuperSection (16MB) bit */ 173 #define L1_S_V6_XN L1_S_IMP /* ARMv6 eXecute Never */ 174 #define L1_S_V6_APX 0x00008000 /* ARMv6 AP eXtension */ 175 #define L1_S_V6_S 0x00010000 /* ARMv6 Shared */ 176 #define L1_S_V6_nG 0x00020000 /* ARMv6 not-Global */ 177 #define L1_S_V6_SS 0x00040000 /* ARMv6 SuperSection */ 178 #define L1_S_V6_NS 0x00080000 /* ARMv6 Not Secure */ 179 180 /* L1 Coarse Descriptor */ 181 #define L1_C_IMP0 0x00000004 /* implementation defined */ 182 #define L1_C_IMP1 0x00000008 /* implementation defined */ 183 #define L1_C_IMP2 0x00000010 /* implementation defined */ 184 #define L1_C_DOM(x) ((x) << 5) /* domain */ 185 #define L1_C_DOM_MASK L1_C_DOM(0xf) 186 #define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 187 188 #define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */ 189 #define L1_C_V6_P 0x00000200 /* ECC enable for this section */ 190 191 /* L1 Fine Descriptor */ 192 #define L1_F_IMP0 0x00000004 /* implementation defined */ 193 #define L1_F_IMP1 0x00000008 /* implementation defined */ 194 #define L1_F_IMP2 0x00000010 /* implementation defined */ 195 #define L1_F_DOM(x) ((x) << 5) /* domain */ 196 #define L1_F_DOM_MASK L1_F_DOM(0xf) 197 #define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */ 198 199 #define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */ 200 201 /* 202 * ARM L2 Descriptors 203 */ 204 205 #define L2_TYPE_INV 0x00 /* Invalid (fault) */ 206 #define L2_TYPE_L 0x01 /* Large Page */ 207 #define L2_TYPE_S 0x02 /* Small Page */ 208 #define L2_TYPE_T 0x03 /* Tiny Page (not armv7) */ 209 #define L2_TYPE_MASK 0x03 /* mask of type bits */ 210 211 /* 212 * This L2 Descriptor type is available on XScale processors 213 * when using a Coarse L1 Descriptor. The Extended Small 214 * Descriptor has the same format as the XScale Tiny Descriptor, 215 * but describes a 4K page, rather than a 1K page. 216 * For V6 MMU, this is used when XP bit is cleared. 217 */ 218 #define L2_TYPE_XS 0x03 /* XScale/ARMv6 Extended Small Page */ 219 220 #define L2_B 0x00000004 /* Bufferable page */ 221 #define L2_C 0x00000008 /* Cacheable page */ 222 #define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ 223 #define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ 224 #define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ 225 #define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ 226 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 227 228 #define L2_XS_L_TEX(x) ((x) << 12) /* Type Extension */ 229 #define L2_XS_T_TEX(x) ((x) << 6) /* Type Extension */ 230 #define L2_XS_XN 0x00000001 /* ARMv6 eXecute Never (when XP=1) */ 231 #define L2_XS_APX 0x00000200 /* ARMv6 AP eXtension */ 232 #define L2_XS_S 0x00000400 /* ARMv6 Shared */ 233 #define L2_XS_nG 0x00000800 /* ARMv6 Not-Global */ 234 #define L2_V6_L_TEX L2_XS_L_TEX 235 #define L2_V6_XS_TEX L2_XS_T_TEX 236 #define L2_XS_L_XN 0x00008000 /* ARMv6 eXecute Never */ 237 238 239 /* 240 * Access Permissions for L1 and L2 Descriptors. 241 */ 242 #define AP_W 0x01 /* writable */ 243 #define AP_U 0x02 /* user */ 244 245 /* 246 * Access Permissions for L1 and L2 of ARMv6 with XP=1 and ARMv7 247 */ 248 #define AP_R 0x01 /* readable */ 249 #define AP_RO 0x20 /* read-only (L2_XS_APX >> 4) */ 250 251 /* 252 * Short-hand for common AP_* constants. 253 * 254 * Note: These values assume the S (System) bit is set and 255 * the R (ROM) bit is clear in CP15 register 1. 256 */ 257 #define AP_KR 0x00 /* kernel read */ 258 #define AP_KRW 0x01 /* kernel read/write */ 259 #define AP_KRWUR 0x02 /* kernel read/write user read */ 260 #define AP_KRWURW 0x03 /* kernel read/write user read/write */ 261 262 /* 263 * Note: These values assume the S (System) and the R (ROM) bits are clear and 264 * the XP (eXtended page table) bit is set in CP15 register 1. ARMv6 only. 265 */ 266 #define APX_KR(APX) (APX|0x01) /* kernel read */ 267 #define APX_KRUR(APX) (APX|0x02) /* kernel read user read */ 268 #define APX_KRW(APX) ( 0x01) /* kernel read/write */ 269 #define APX_KRWUR(APX) ( 0x02) /* kernel read/write user read */ 270 #define APX_KRWURW(APX) ( 0x03) /* kernel read/write user read/write */ 271 272 /* 273 * Note: These values are for the simplified access permissions model 274 * of ARMv7. Assumes that AFE is clear in CP15 register 1. 275 * Also used for ARMv6 with XP bit set. 276 */ 277 #define AP7_KR 0x21 /* kernel read */ 278 #define AP7_KRUR 0x23 /* kernel read user read */ 279 #define AP7_KRW 0x01 /* kernel read/write */ 280 #define AP7_KRWURW 0x03 /* kernel read/write user read/write */ 281 282 /* 283 * Domain Types for the Domain Access Control Register. 284 */ 285 #define DOMAIN_FAULT 0x00 /* no access */ 286 #define DOMAIN_CLIENT 0x01 /* client */ 287 #define DOMAIN_RESERVED 0x02 /* reserved */ 288 #define DOMAIN_MANAGER 0x03 /* manager */ 289 290 /* 291 * Type Extension bits for XScale processors. 292 * 293 * Behavior of C and B when X == 0: 294 * 295 * C B Cacheable Bufferable Write Policy Line Allocate Policy 296 * 0 0 N N - - 297 * 0 1 N Y - - 298 * 1 0 Y Y Write-through Read Allocate 299 * 1 1 Y Y Write-back Read Allocate 300 * 301 * Behavior of C and B when X == 1: 302 * C B Cacheable Bufferable Write Policy Line Allocate Policy 303 * 0 0 - - - - DO NOT USE 304 * 0 1 N Y - - 305 * 1 0 Mini-Data - - - 306 * 1 1 Y Y Write-back R/W Allocate 307 */ 308 #define TEX_XSCALE_X 0x01 /* X modifies C and B */ 309 310 /* 311 * Type Extension bits for ARM V6 and V7 MMU 312 * 313 * TEX C B Shared 314 * 000 0 0 Strong order yes 315 * 000 0 1 Shared device yes 316 * 000 1 0 Outer and Inner write through, no write alloc S-bit 317 * 000 1 1 Outer and Inner write back, no write alloc S-bit 318 * 001 0 0 Outer and Inner non-cacheable S-bit 319 * 001 0 1 reserved 320 * 001 1 0 reserved 321 * 001 1 1 Outer and Inner write back, write alloc S-bit 322 * 010 0 0 Non-shared device no 323 * 010 0 1 reserved 324 * 010 1 X reserved 325 * 011 X X reserved 326 * 1BB A A BB for inner, AA for outer S-bit 327 * 328 * BB inner cache 329 * 0 0 Non-cacheable 330 * 0 1 Write back, write alloc 331 * 1 0 Write through, no write alloc 332 * 1 1 Write back, no write alloc 333 * 334 * AA outer cache 335 * 0 0 Non-cacheable 336 * 0 1 Write back, write alloc 337 * 1 0 Write through, no write alloc 338 * 1 1 Write back, no write alloc 339 */ 340 341 #define TEX_ARMV6_TEX 0x07 /* 3 bits in TEX */ 342 343 #endif /* _ARM_PTE_H_ */ 344
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